STM6600AS24DM6F datasheet(9/51 Pages) STMICROELECTRONICS

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STM6600 - STM6601

Pin descriptions

Doc ID 15453 Rev 7

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Pin descriptions

VCC - power supply input

VCC is monitored during startup and normal operation for sufficient voltage level. Decouple

the VCC pin from ground by placing a 0.1 µF capacitor as close to the device as possible.

SR - Smart Reset™ button input

This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV

HBM ESD protection.

Both PB and SR buttons have to be pressed and held for tSRD period so the long push is

recognized and the reset is asserted (or the enable output is deasserted depending on the

option) - see Figure 15, 16, and 17.

Active low SR input is usually connected to GND through the momentary push-button (see

Figure 1) and it has an optional 100 k

Ω pull-up resistor. It is also possible to drive this input

using an external device with either open drain (recommended) or push-pull output. Open

drain output can be connected in parallel with push-button or other open drain outputs,

which is not possible with push-pull output.

VREF - external precise 1.5 V voltage reference

This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has

proper output voltage as soon as the reset output is deasserted (i.e. after tREC expires) and

it is disabled when the device enters standby mode. A mandatory capacitor needs to be

connected to VREF output (even if VREF is not used). Capacitor value of 1 µF is

recommended.

PSHOLD input

This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to

confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown

(if EN or EN is asserted).

Forcing PSHOLD high during power-up confirms the proper start of the application and keeps

enable output asserted. Because most processors have outputs in high-Z state before

initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see

Figure 7, 8, 9, 10, 11, 12, 13, and 18).

Forcing the PSHOLD signal low during normal operation deasserts the enable output (see

Figure 14). Input voltage on this pin is compared to an accurate voltage reference.

CSRD - Smart Reset

™delay time input

A capacitor to ground determines the additional time (tSRD) that PB with SR must be

pressed and held before a long push is recognized. The connected CSRD capacitor is

charged with ISRD current. Additional Smart Reset

™ delay time t

SRD ends when voltage on

the CSRD capacitor reaches the VSRD voltage threshold. It is recommended to use a low

ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the CSRD pin open. If no

capacitor is connected, there is no tSRD and a long push is recognized right after tINT_Min

expires (see Figure 18 and 19).

STM6600AS24DM6F 数据表(PDF) 9 Page - STMicroelectronics

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