HT83F60 datasheet(14/62 Pages) HOLTEK

14 / 62 page

HT83FXX

Rev. 1.30

June 7, 2010

time-out or by executing the

²CLR WDT² or ²HALT² in-

struction. The PDF flag is affected only by executing the

²HALT² or ²CLR WDT² instruction or during a system

power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

· C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place dur-

ing a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

· AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

· Z is set if the result of an arithmetic or logical operation

is zero; otherwise Z is cleared.

· OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

· PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

· TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the subroutine

can corrupt the status register, precautions must be

taken to correctly save it.

Interrupt Control Register

- INTC, INTCH

Two 8-bit register, known as the INTC and INTCH regis-

ters, controls the operation of both external and internal

timer interrupts. By setting various bits within these reg-

isters using standard bit manipulation instructions, the

enable/disable function of the external and timer inter-

rupts can be independently controlled. A master inter-

rupt bit within this register, the EMI bit, acts like a global

enable/disable and is used to set all of the interrupt en-

able bits on or off. This bit is cleared when an interrupt

routine is entered to disable further interrupt and is set

by executing the

²RETI² instruction.

Note: In situations where other interrupts may require

servicing within present interrupt service rou-

tines, the EMI bit can be manually set by the pro-

gram after the present interrupt service routine

has been entered.

Timer Registers

All devices contain two 8-bit Timers whose associated

registers are known as TMR0 and TMR1 which is the lo-

cation where the associated timer's 8-bit value is lo-

cated. Their associated control registers, known as

TMR0C and TMR1C, contain the setup information for

these timers.

Note that all timer registers can be directly written to in

order to preload their contents with fixed data to allow

different time intervals to be setup.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PB etc. These labeled

I/O registers are mapped to specific addresses within

the Data Memory as shown in the Data Memory table,

which are used to transfer the appropriate output or in-

put data on that port. With each I/O port there is an asso-

ciated control register labeled PAC, PBC, etc., also

mapped to specific addresses with the Data Memory.

The control register specifies which pins of that port are

set as inputs and which are set as outputs. To setup a

pin as an input, the corresponding bit of the control reg-

ister must be set high, for an output it must be set low.

During program initialisation, it is important to first setup

the control registers to specify which pins are outputs

and which are inputs before reading data from or writing

data to the I/O ports. One flexible feature of these regis-

ters is the ability to directly program single bits using the

²SET [m].i² and ²CLR [m].i² instructions. The ability to

change I/O pins from output to input and vice-versa by

manipulating specific bits of the I/O control registers dur-

ing normal program operation is a useful feature of

these devices.

T O

P D F

O V

A C

S T A T U S R e g i s t e r

A r i t h m e t i c / L o g i c O p e r a t i o n F l a g s

C a r r y f l a g

A u x i l i a r y c a r r y f l a g

Z e r o f l a g

O v e r f l o w f l a g

S y s t e m M a n a g e m e n t F l a g s

P o w e r d o w n f l a g

W a t c h d o g t i m e - o u t f l a g

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

b 0

Status Register

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