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HT83F60 数据表(PDF) 43 Page - Holtek Semiconductor Inc |
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HT83F60 数据表(HTML) 43 Page - Holtek Semiconductor Inc |
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43 / 62 page ![]() HT83FXX Rev. 1.30 43 June 7, 2010 Voice Output The device contains an internal 12-bit DAC function which can be used for audio signal generation. Voice Control Two internal registers DAL and DAH contain the 12-bit digital value for conversion by the internal DAC. There is also a DAC enable/disable control bit in the PWMC con- trol register for overall on/off control of the DAC circuit. If the DAC circuit is not enabled, the DAH/DAL value out- puts will be invalid. Writing a ²1² to the DAC bit in bit1 of PWMCR will enable the enable DAC circuit, while writ- ing a ²0² to the DAC bit will disable the DAC circuit. Audio Output and Volume Control - DAL, DAH, VOL The audio output is 12-bits wide whose highest 8-bits are written into the DAH register and whose lowest four bits are written into the highest four bits of the DAL regis- ter. Bits 0~3 of the DAL register are always read as zero. There are 8 levels of volume which are setup using the VOL register. Only the lowest 3-bits of this register are used for volume control. 8 - b i t C o u n t e r ( ¸ 2 5 6 ) 7 - b i t P r e s c a l e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 W D T C l o c k S o u r c e C l e a r W D T T y p e C o n f i g u r a t i o n O p t i o n C L R W D T 1 F l a g C L R W D T 2 F l a g 1 o r 2 I n s t r u c t i o n s C L R C L R f S Y S / 4 W D T O s c i l l a t o r W D T C l o c k S o u r c e C o n f i g u r a t i o n O p t i o n Watchdog Timer D A L R e g i s t e r b 7 b 0 N o t u s e d , r e a d a s " 0 " D 3 D 2 D 1 D 0 A u d i o o u t p u t D A L R e g i s t e r D A H R e g i s t e r b 7 b 0 D 1 1 D 1 0 D 9 D 8 A u d i o o u t p u t D A H R e g i s t e r V o i c e C o n t r o l R e g i s t e r D 7 D 6 D 5 D 4 V O L R e g i s t e r b 7 b 0 N o t u s e d , r e a d a s " 0 " V 0 V 1 V 2 V 3 V O L 2 V O L 1 V O L 0 P W M v o l u m e c o n t r o l D A C v o l u m e c o n t r o l W S 2 W D T S R e g i s t e r b 7 b 0 W D T p r e s c a l e r r a t e s e l e c t W S 2 0 0 0 0 1 1 1 1 W S 1 0 0 1 1 0 0 1 1 W S 0 0 1 0 1 0 1 0 1 W D T R a t e 1 : 1 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4 1 : 1 2 8 N o t u s e d W S 1 W S 0 Watchdog Timer Register |
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