HT83F60 datasheet(25/62 Pages) HOLTEK

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HT83FXX

Rev. 1.30

June 7, 2010

Master/Salve

(SIMEN=0)

Master (SIMEN=1)

Slave (SIMEN=1)

CSEN=1

CSEN=0

SCS line=0

(CSEN=1)

SCS line=1

(CSEN=1)

SCS

I, Z

SDO

OOOO

SDI

I, Z

SCK

L(CPOL=1)

H(CPOL=0)

L(CPOL=1)

H(CPOL=0)

I, Z

²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)

SPI Interface Pin Status

· SPI Registers

The SIMDR register is used to store the data being

transmitted and received. There are two control regis-

ters associated with the SPI interface, SIMC0 and

SIMC2 and one data register known as SIMDR. The

SIMC1 register is not used by the SPI function. Regis-

ter SIMC0 is used to control the enable/disable func-

tion, the power down control and to set the data

transmission clock frequency. Register SIMC2 is used

for other control functions such as LSB/MSB selec-

tion, write collision flag etc.

The following gives further explanation of each bit:

¨ SIMEN

The SIMEN bit is the overall on/off control for the

SPI interface. When the SIMENbit is cleared to zero

to disable the SPI interface, the SDI, SDO, SCK and

SCS lines will be in a floating condition and the SPI

operating current will be reduced to <0.1

mAat 5V.

When the bit is high the SPI interface is enabled.

Note that when the SIMEN bit changes from low to

high the contents of the SPI control registers will be

in an unknown condition and should therefore be in-

itialised by the application program.

¨ SIM0~SIM2

These three bits control the Master/Slave selection

and also setup the SPI interface clock speed when

in the Master Mode. The SPI clock is a function of

the system clock whether it be RC type or Crystal

type. If the Slave Mode is selected then the clock

will be supplied by the external Master device.

The following gives further explanation of each bit:

¨ TRF

The TRF bit is the Transmit/Receive Complete flag

and is cleared by the application program and can

be used to generate an interrupt. When the bit is

high the data has been transmitted or received. If

the bit is low the data is being transmitted or has not

yet been received.

¨ WCOL

The WCOL bit is used to detect if a data collision

has occurred. If this bit is high it means that data

has been attempted to be written to the SMDR reg-

ister during a data transfer operation. This writing

operation will be ignored if data is being transferred.

The bit can be cleared by the application program.

Note that using the CSEN bit can be disabled or en-

abled via configuration option.

¨ CSEN

The CSEN bit is used as an on/off control for the

SCS pin. If this bit is low then the SCS pin will be dis-

abled and placed into a floating condition. If the bit is

high the SCS pin will be enabled and used as a se-

lect pin.

¨ MLS

The MLS is used to select how the data is trans-

ferred, either MSB or LSB first. Setting the bit high

will select MSB first and low for LSB first.

Note that the SIMC2 register is the same as the

SIMAR register used by the I

2C interface.

· SPI Communication

After the SPI interface is enabled by setting the

SIMEN bit high, then in the Master Mode, when data is

written to the SIMDR register, transmission/reception

will begin simultaneously. When the data transfer is

complete, the TRF flag will be set automatically. In the

Slave Mode, when the clock signal from the master

has been received, any data in the SIMDR register will

be transmitted and any data on the SDI pin will be

shifted into the SIMDR register. The master should

output an SCS signal before a clock signal is provided

and slave data transfers should be enabled/disabled

before/after an SCS signal is received.

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