PIC16F526-ISLASHP datasheet(23/122 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41326D-page 23

PIC16F526

5.0

FLASH DATA MEMORY

CONTROL

The Flash data memory is readable and writable during

normal operation (full VDD range). This memory is not

directly mapped in the register file space. Instead, it is

indirectly addressed through the Special Function

Registers (SFRs).

5.1

Reading Flash Data Memory

To read a Flash data memory location the user must:

• Write the EEADR register

• Set the RD bit of the EECON register

The value written to the EEADR register determines

which Flash data memory location is read. Setting the

RD bit of the EECON register initiates the read. Data

from the Flash data memory read is available in the

EEDATA register immediately. The EEDATA register

will hold this value until another read is initiated or it is

modified by a write operation. Program execution is

suspended while the read cycle is in progress.

Execution will continue with the instruction following the

one that sets the WR bit. See Example 1 for sample

code.

EXAMPLE 1:

READING FROM FLASH

DATA MEMORY

5.2

Writing and Erasing Flash Data

Memory

Flash data memory is erased one row at a time and

written one byte at a time. The 64-byte array is made

up of eight rows. A row contains eight sequential bytes.

Row boundaries exist every eight bytes.

Generally, the procedure to write a byte of data to Flash

data memory is:

Identify the row containing the address where

the byte will be written.

If there is other information in that row that must

be saved, copy those bytes from Flash data

memory to RAM.

Perform a row erase of the row of interest.

Write the new byte of data and any saved bytes

back to the appropriate addresses in Flash data

memory.

To prevent accidental corruption of the Flash data

memory, an unlock sequence is required to initiate a

write or erase cycle. This sequence requires that the bit

set instructions used to configure the EECON register

happen exactly as shown in Example 2 and Example 3,

depending on the operation requested.

5.2.1

ERASING FLASH DATA MEMORY

A row must be manually erased before writing new

data. The following sequence must be performed for a

single row erase.

Load EEADR with an address in the row to be

erased.

Set the FREE bit to enable the erase.

Set the WREN bit to enable write access to the

array.

Set the WR bit to initiate the erase cycle.

If the WREN bit is not set in the instruction cycle after

the FREE bit is set, the FREE bit will be cleared in

hardware.

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

Sample code that follows this procedure is included in

Example 2.

Program execution is suspended while the erase cycle

is in progress. Execution will continue with the

instruction following the one that sets the WR bit.

EXAMPLE 2:

ERASING A FLASH DATA

MEMORY ROW

Note: Only a BSF command will work to enable the

Flash data memory read documented in

Example 1.

other

sequence

commands will work, no exceptions.

BANKSEL EEADR

;

MOVF DATA_EE_ADDR, W

;

MOVWF EEADR

;Data Memory

;Address to read

BANKSEL EECON1

;

BSF EECON, RD

;EE Read

MOVF EEDATA, W

;W = EEDATA

Note 1: The FREE bit may be set by any com-

mand normally used by the core. How-

ever, the WREN and WR bits can only be

set using a series of BSF commands, as

documented in Example 1. No other

sequence of commands will work, no

exceptions.

2: Bits <5:3> of the EEADR register indicate

which row is to be erased.

BANKSEL

EEADR

MOVLW

EE_ADR_ERASE

; LOAD ADDRESS OF ROW TO

; ERASE

MOVWF

EEADR

;

BSF

EECON,FREE

; SELECT ERASE

BSF

EECON,WREN

; ENABLE WRITES

BSF

EECON,WR

; INITITATE ERASE

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