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PIC16F526-I/P 数据表(PDF) 16 Page - Microchip Technology |
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PIC16F526-I/P 数据表(HTML) 16 Page - Microchip Technology |
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16 / 122 page  PIC16F526 DS41326D-page 16 2010 Microchip Technology Inc. 4.2 Data Memory (SRAM and FSRs) Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The Special Function Registers are registers used by the CPU and peripheral functions for controlling desired operations of the PIC16F526. See Figure 4-1 for details. The PIC16F526 register file is composed of 16 Special Function Registers and 67 General Purpose Registers. 4.2.1 GENERAL PURPOSE REGISTER FILE The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.8 “Indirect Data Addressing: INDF and FSR Registers”. 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. FIGURE 4-2: REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 1Fh INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB 10h Bank 0 Bank 1 Bank 2 Bank 3 3Fh 30h 20h 5Fh 50h 40h 7Fh 70h 60h General Purpose Registers General Purpose Registers General Purpose Registers General Purpose Registers General Purpose Registers PORTC 08h Note 1: Not a physical register. See Section 4.8 “Indirect Data Addressing: INDF and FSR Registers”. FSR<6:5> 00 01 10 11 2Fh 4Fh 6Fh 0Dh CM1CON0 CM2CON0 VRCON 09h 0Ah 0Bh ADRES ADCON0 0Ch 0Fh INDF(1) EECON PCL STATUS FSR EEDATA EEADR CM1CON0 CM2CON0 VRCON ADRES ADCON0 INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB PORTC VRCON ADRES ADCON0 INDF(1) EECON PCL STATUS FSR EEDATA EEADR VRCON ADRES ADCON0 CM1CON0 CM1CON0 CM2CON0 CM2CON0 PORTC PORTC Addresses map back to addresses in Bank 0. |
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