MC68HC705MC4MP datasheet(60/180 Pages) FREESCALE

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Operating Modes

MC68HC705MC4 — Rev. 2.0

Operating Modes

6.4.3 Mask Option Register

This register is latched upon RESET and at regular intervals as

determined by the COP timeout period. The register is an EPROM byte

located at $0F00 and holds the option bit for COP disable/enable.

COPE — COP Enable/Disable

1 = The COP is enabled.

0 = (erased state) The COP is disabled.

NOTE:

The COPE bit is not readable.

6.5 Low-Power Mode

MC68HC705MC4 is capable of running in a low-power mode in each of

its configurations. The WAIT instruction reduces the power required for

the MCU by stopping various internal clocks and/or the on-chip

oscillator. The WAIT instruction is not normally used if the COP

watchdog timer is enabled. Execution of the stop instruction will take the

effect of a NOP. The flow of wait mode is shown in Figure 6-6.

NOTE:

The ROM option will include the STOP functions.

Address:

$0F00

Bit 7

654321

Bit 0

Read:

UUUUUUU

Write:

COPE

Erased:

00000000

= Undetermined

= Unimplemented

Figure 6-5. Mask Option Register (MOR)

Freescale Semiconductor, Inc.

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