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数据搜索系统，热门电子元器件搜索 |
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MC68HC705MC4MP 数据表(PDF) 93 Page - Freescale Semiconductor, Inc |
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MC68HC705MC4MP 数据表(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 180 page  16-Bit Timer Timer Operation during Wait/Halt Modes General Release Specification 16-Bit Timer ICF1 — Input Capture 1 Flag Bit 6 is set when the edge specified by IEDG1 in register TCR has been sensed by the input capture edge detector fed by pin TCAP1. This flag, and the input capture interrupt, can be cleared by reading register TSR followed by reading the LSB of the input capture register pair (ICRL1). TOF — Timer Overflow Flag Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This flag, and the timer overflow interrupt, can be cleared by reading register TSR followed by reading the LSB of the timer register pair (TMRL). OCF — Output Compare Flag Bit 4 is set when the contents of the output compare registers match the contents of the free-running counter. This flag, and the output compare interrupt, can be cleared by reading register TSR followed by writing the LSB of the output compare register pair (OCRL). 9.8 Timer Operation during Wait/Halt Modes During wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the wait mode. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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