MC68HC705MC4MP datasheet(98/180 Pages) FREESCALE

98 / 180 page

Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

The RATE register selects the PWM counter input clock rate, defining

the PWM period. This register is buffered but not interlocked with other

registers. Therefore, writes to the RATE register will become effective

immediately (if the corresponding update bit has been set) or at the end

of the current PWM period (if the corresponding update bit has been

cleared), irrespective of the state of any interlock mechanism.

Figure 10-2. PWM Register Structure

WRITE

ALL WRITES WRITE TO THE BUFFER REGISTERS

TRANSFER ENABLES AT END OF PWMB PERIOD

ALL READS READ FROM THE EFFECTIVE REGISTERS

TRANSFER ENABLES AT END OF PWMA PERIOD

WRITE

$14

READ

$14

CTL-A EFFECTIVE)

CTL-A (BUFFER)

WRITE

$15

READ

$15

CTL-B (EFFECTIVE)

CTL-B (BUFFER)

WRITE

$16

READ

$16

RATE (EFFECTIVE)

RATE (BUFFER)

$10

READ

$10

DATA-A (EFFECTIVE)

DATA-A (BUFFER)

WRITE

$12

READ

$12

DATA-B (EFFECTIVE)

DATA-B(BUFFER)

$11

$13

$11

$13

*Subject to satisfying interlock conditions and the state of the corresponding UPDATE bit

Freescale Semiconductor, Inc.

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