MC68HC705MC4MP datasheet(86/180 Pages) FREESCALE

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16-Bit Timer

MC68HC705MC4 — Rev. 2.0

16-Bit Timer

Figure 9-6. Output Compare Software Initialization Example

Figure 9-7. State Timing Diagram for Output Compare

SEI

LDA

LDX

STA

LDA

STX

CLI

DATAH

DATAL

OCRH

TSR

OCRL

BLOCK INTERRUPTS

HI BYTE FOR COMPARE

LO BYTE FOR COMPARE

INHIBIT OUTPUT COMPARE

ARM OCF BIT TO CLEAR

READY FOR NEXT COMPARE

UNBLOCK INTERRUPTS

INTERNAL

TIMER

T00

T01

T10

T11









OUTPUT COMPARE

16-BIT

$FFEB

$FFED

$FFEE

$FFEC

OUTPUT COMPARE

$FFED

CPU WRITES $FFED

$FFEF

FLAG AND PIN

REGISTERS

NOTES:

1. A write to the output compare registers may occur at any time, but a compare only occurs at

timer state T01. Therefore, the compare may follow the write by up to four cycles.

2. The output compare ﬂag is set at the timer state T11 that follows the comparison latch.

BUS CLOCK

CLOCKS

COUNTER

COMPARE

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