 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADIS16133/PCBZ 数据表(PDF) 4 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADIS16133/PCBZ 数据表(HTML) 4 Page - Analog Devices |
|
|
4 / 20 page  ADIS16133 Rev. 0 | Page 4 of 20 TIMING SPECIFICATIONS TA = 25°C, VCC = 5 V, unless otherwise noted. Table 2. Normal Mode Parameter Description Min1 Typ Max Unit f SCLK Serial clock 0.01 2.0 MHz t STALL Stall period between data 9 µs t READRATE Read rate 25 µs t CS Chip select to clock edge 48.8 ns t DAV DOUT valid after SCLK edge 25 ns t DSU DIN setup time before SCLK rising edge 24.4 ns t DHD DIN hold time after SCLK rising edge 48.8 ns t SCLKR, tSCLKF SCLK rise/fall times 5 12.5 ns t DR, tDF DOUT rise/fall times 5 12.5 ns t SFS CS high after SCLK edge 0 ns t 1 Input sync positive pulse width 5 µs t x Input sync low time 100 µs t 2 Input sync to data ready output 360 µs t 3 Input sync period 488 µs 1 Guaranteed by design and characterization but not tested in production. Timing Diagrams CS SCLK DOUT DIN 1 2 3 4 5 6 15 16 R/W A5 A6 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tSFS tDAV tDHD tDSU Figure 2. SPI Timing and Sequence CS SCLK tREADRATE tSTALL Figure 3. Stall Time and Data Rate t3 tX t2 t1 SYNC CLOCK (CLKIN) DATA READY Figure 4. Input Clock Timing Diagram |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
