ADIS16133

Rev. 0 | Page 14 of 20

SYSTEM CONTROLS

The ADIS16133 provides a number of system level controls for

managing its operation using the registers listed in Table 28.

Table 28. System Tool Registers

Register Name

Address

Description

FLASH_CNT

0x00

Flash write cycle counter

GPIO_CTRL

0x1A

General-purpose I/O control

MSC_CTRL

0x1C

Self-test, calibration, data ready

SLP_CTRL

0x24

Sleep mode control

DIAG_STAT

0x26

Error flags

GLOB_CMD

0x28

Single command functions

LOT_ID1

0x32

Lot Identification Code 1

LOT_ID2

0x34

Lot Identification Code 2

LOT_ID3

0x36

Lot Identification Code 3

PROD_ID

0x38

Product identification

SERIAL_NUM

0x3A

Serial number

GLOBAL COMMANDS

The GLOB_CMD register (see Table 29) provides trigger bits

for several operations. Write 1 to the appropriate bit in the

GLOB_CMD register to start a function. After the function

completes, the bit restores to 0.

Software Reset

Set GLOB_CMD[7] = 1 (DIN = 0xA880) to reset the operation,

which removes all data, initializes all registers from their flash

settings, and starts data collection. This function provides a

firmware alternative to the RST line (see Table 5, Pin 8).

Table 29. GLOB_CMD Bit Descriptions

Bits

Description

Execution Time1

[15:8]

Not used

N/A2

[7]

Software reset

71 ms

[6:4]

Not used

N/A2

[3]

Flash update

72 ms

[2]

Not used

N/A2

[1]

Factory calibration restore

72 ms

[0]

Automatic bias correction

N/A2

the next data ready pulse, restarts the decimation cycle, and then writes to

the flash 72 ms) after completing a decimation cycle. With respect to Figure 18,

MEMORY MANAGEMENT

The data retention of the flash memory has a dependency on

temperature, as shown in Figure 20. The FLASH_CNT register

(see Table 30) provides a 16-bit counter that helps track the

number of write cycles to the nonvolatile flash memory, which

helps manage the endurance rating. The flash updates every

time any of the following bits are set to 1: GLOB_CMD[3],

GLOB_CMD[1], and GLOB_ CMD[0].

Table 30. FLASH_CNT Bit Descriptions

Bits

Description

[15:0]

Binary counter; number of flash updates

600

450

300

150

0

30

40

JUNCTION TEMPERATURE (°C)

55

70

85

100

125

135

150

Figure 20. Flash Memory Retention

Checksum Test

Set MSC_CTRL[11] = 1 (DIN = 0x9D08) to perform a checksum

verification of the internal program memory. This takes a sum-

mation of the internal program memory and compares it with

the original summation value for the same locations (from

factory configuration). Check the results in the DIAG_STAT

register (see Table 34). DIAG_STAT[6] equals 0 when the sum

matches the correct value and it equals 1 when it does not. Make

sure that the power supply is within specification for the entire

20 ms that this function takes to complete.

GENERAL-PURPOSE INPUT/OUTPUT

There are two general-purpose I/O lines, DIO1 and DIO2, which

provide a number of useful functions. The MSC_CTRL[2:0] bits

(see Table 31) control the data ready configuration and have the

highest priority for setting either DIO1 or DIO2 (but not both).

The ALM_CTRL[2:0] control bits (see Table 26) provide the

alarm indicator configuration control and have the second

highest priority for DIO1 or DIO2. When DIO1 and DIO2 are

not in use as either data ready or alarm indicator signals, the

GPIO_CTRL register (see Table 32) provides the control and

data bits for them.

Data Ready I/O Indicator

The factory default setting for MSC_CTRL[2:0] is 110, which

configures DIO1 as a positive data ready indicator signal. A

common option for this function is MSC_CTRL[2:0] = 100

(DIN = 0x9C04), which changes data ready to a negative

polarity for processors that provide only negative triggered

interrupt pins. The pulse width is between 100 μs and 200 μs

over all conditions.