PIC18F23K22-ESLASHML datasheet(39/496 Pages) MICROCHIP

39 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 39

PIC18(L)F2X/4XK22

2.6

PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated frequency from the crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals or users who require higher

clock speeds from an internal oscillator.

2.6.1

PLL IN EXTERNAL OSCILLATOR

MODES

The PLL can be enabled for any of the external

oscillator modes using the OSC1/OSC2 pins by either

setting the PLLCFG bit (CONFIG1H<4>), or setting the

PLLEN bit (OSCTUNE<6>). The PLL is designed for

input frequencies of 4 MHz up to 16 MHz. The PLL then

multiplies the oscillator output frequency by 4 to

produce an internal clock frequency up to 64 MHz.

Oscillator frequencies below 4 MHz should not be used

with the PLL.

2.6.2

PLL IN HFINTOSC MODES

The 4x frequency multiplier can be used with the

internal oscillator block to produce faster device clock

speeds than are normally possible with the internal

oscillator. When enabled, the PLL multiplies the

HFINTOSC by 4 to produce clock rates up to 64 MHz.

Unlike external clock modes, the PLL can only be

controlled through software. The PLLEN control bit of

the OSCTUNE register is used to enable or disable the

PLL operation when the HFINTOSC is used.

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