Application hints

LIS331DLF

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Doc ID 15101 Rev 4

4

Application hints

Figure 5.

LIS331DLF electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Aluminum) should

be placed as near as possible to the pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to

Figure 5). It is possible to remove Vdd maintaining Vdd_IO

without blocking the communication bus, in this condition the measurement chain is

powered off.

The functionality of the device and the measured acceleration data is selectable and

The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be

4.1

Soldering information

It is qualified for soldering heat resistance according to JEDEC J-STD-020C.

Leave “pin 1 indicator” unconnected during soldering.

10µF

Vdd

100nF

GND

Vdd_IO

INT 1

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

1

5

8

13

TOP VIEW

6

9

14

16

9

5

INT 2