LIS331DLF datasheet(25/38 Pages) STMICROELECTRONICS

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LIS331DLF

Doc ID 15101 Rev 4

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The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The registers address, made of 7 bits, is used to identify them and to

write the data through serial interface.

7.1

WHO_AM_I (0Fh)

Device identification register.

This register contains the device identifier that for LIS331DLF is set to 52h.

7.2

CTRL_REG1 (20h)

PM bits allow to select between power-down and two operating active modes. The device is

in power-down mode when PD bits are set to “000” (default value after boot).

Table 19

shows all the possible power mode configurations and respective output data rates. Output

data in the low-power modes are computed with low-pass filter cut-off frequency defined by

DR1, DR0 bits.

DR bits, in the normal-mode operation, select the data rate at which acceleration samples

are produced. In low-power mode they define the output data resolution.

Table 20 shows all

the possible configuration for DR1 and DR0 bits.

Table 16.

WHO_AM_I register

101

Table 17.

CTRL_REG1 register

PM2

PM1

PM0

DR1

DR0

Zen

Yen

Xen

Table 18.

CTRL_REG1 description

PM2 - PM0

Power mode selection. Default value: 000

(000: Power-down; Others: refer to

Table 19)

DR1, DR0

Data rate selection. Default value: 00

(00:50 Hz; Others: refer to

Table 20)

Zen

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen

Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

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