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325 数据表(PDF) 26 Page - Intel Corporation |
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325 数据表(HTML) 26 Page - Intel Corporation |
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26 / 82 page  26 Datasheet Electrical Specifications Table 2-10. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL Input Low Voltage 0.0 GTLREF – (0.10 * VCC)V 2,3 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VCC referred to in these specifications is the instantaneous VCC. VIH Input High Voltage GTLREF + (0.10 * VCC)VCC V 3,4,5 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VCC. VOH Output High Voltage 0.90*VCC VCC V 3,5 IOL Output Low Current N/A VCC/ [0.50*RRTT_MIN+RON_MIN] A ILI Input Leakage Current N/A ± 200 µA 6 6. Leakage to VSS with pin held at VCC. ILO Output Leakage Current N/A ± 200 µA 7 7. Leakage to VCC with pin held at 300 mV. Ron_compatible Buffer On Resistance 6.33 10.33 Ω 8 8. These specifications are different depending on whether the platform is forward compatible to the Celeron D proces- sor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous gen- eration processor but has some level of compatibility with the Celeron D processor. An optimized platform is one designed specifically for the Celeron D processor; however, it may have some level of compatibility with previous generation processors. Ron_optimized Buffer On Resistance 8 12 Ω 8 Table 2-11. Asynchronous GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. VIL Input Low Voltage 0.0 VCC/2 – (0.10 * VCC)V 2,3 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals VIH = GTLREF + (0.10 * VCC) and VIL= GTLREF – (0.10 * VCC). VIH Input High Voltage VCC/2 + (0.10 * VCC)VCC V 3,4,5,6 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VCC. 6. The VCC referred to in these specifications refers to instantaneous VCC. VOH Output High Voltage 0.90*VCC VCC V 5,6,7 7. All outputs are open drain. IOL Output Low Current — VCC/[0.50*RTT_MIN+RON_MIN]A 8 8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. IIL Input Leakage Current N/A ± 200 µA 9 9. Leakage to VSS with pin held at VCC. ILO Output Leakage Current N/A ± 200 µA 10 10. Leakage to VCC with pin held at 300 mV. Ron_compatible Buffer On Resistance 6.33 10.33 W 11 Ron_optimized Buffer On Resistance 8 12 W 11 |
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