Clock operations

M48T08, M48T08Y, M48T18

14/31

Doc ID 2411 Rev 10

3

Clock operations

3.1

Reading the clock

prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are

only data registers and not the actual clock counters, so updating the registers can be halted

without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, the seventh bit in the control

register. As long as a '1' remains in that position, updating is halted. After a halt is issued,

the registers reflect the count; that is, the day, date, and the time that were current at the

moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating is within a second after the bit is reset to a '0.'

3.2

Setting the clock

The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the

READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with

the correct day, date, and time data in 24-hour BCD format (on Table 5). Resetting the

WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual

TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits

marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM

operation.

information on century rollover.