STM32F103CBU6TR datasheet(92/96 Pages) STMICROELECTRONICS

92 / 96 page

Revision history

STM32F103x8, STM32F103xB

92/96

Doc ID 13587 Rev 12

22-Nov-2007

Document status promoted from preliminary data to datasheet.

The STM32F103xx is USB certified. Small text changes.

Power supply schemes on page 15 modified. Number of

communication peripherals corrected for STM32F103Tx and number of

GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-

density device features and peripheral counts.

Main function and default alternate function modified for PC14 and

PC15 in, Note 6 added and Remap column added in Table 5: Medium-

density STM32F103xx pin definitions.

VDD–VSS ratings and Note 1 modified in Table 6: Voltage

characteristics, Note 1 modified in Table 7: Current characteristics.

Note 1 and Note 2 added in Table 11: Embedded reset and power

control block characteristics.

IDD value at 72 MHz with peripherals enabled modified in Table 14:

Maximum current consumption in Run mode, code with data

processing running from RAM.

IDD value at 72 MHz with peripherals enabled modified in Table 15:

Maximum current consumption in Sleep mode, code running from

Flash or RAM on page 42.

IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values

added in Table 16: Typical and maximum current consumptions in Stop

and Standby modes. Note added in Table 17 on page 46 and Table 18

on page 47. ADC1 and ADC2 consumption and notes modified in

Table 19: Peripheral current consumption.

tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23,

respectively.

Maximum values removed from Table 26: Low-power mode wakeup

timings. tRET conditions modified in Table 29: Flash memory endurance

and data retention. Figure 13: Power supply scheme corrected.

Figure 19: Typical current consumption in Stop mode with regulator in

Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.

Note removed below Figure 32: SPI timing diagram - slave mode and

CPHA = 0. Note added below Figure 33: SPI timing diagram - slave

mode and CPHA = 1(1).

Details on unused pins removed from General input/output

characteristics on page 58.

Table 41: SPI characteristics updated. Table 42: USB startup time

added. VAIN, tlat and tlatr modified, note added and Ilkg removed in

Table 45: ADC characteristics. Test conditions modified and note added

in Table 48: ADC accuracy. Note added below Table 46 and Table 49.

Inch values corrected in Table 53: LQPF100, 14 x 14 mm 100-pin low-

profile quad flat package mechanical data, Table 54: LQFP64, 10 x 10

mm, 64-pin low-profile quad flat package mechanical data and

Table 56: LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package

mechanical data.



JAvalue for VFQFPN36 package added in Table 57: Package thermal

characteristics



Order codes replaced by Section 7: Ordering information scheme.

MCU ‘s operating conditions modified in Typical current consumption

on page 45. Avg_Slope and V25 modified in Table 49: TS

characteristics. I2C interface characteristics on page 65 modified.

Impedance size specified in A.4: Voltage glitch on ADC input 0 on

page 81.

Table 59.

Document revision history (continued)

Date

Revision

Changes

STM32F103CBU6TR 数据表(PDF) 92 Page - STMicroelectronics

STM32F103CBU6TR 数据表(HTML) 92 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载