PPC8567ECVTANJGA datasheet(122/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

122

Freescale Semiconductor

Clocking

23.2

CCB/SYSCLK PLL Ratio

The CCB clock is the clock that drives the e500 core complex bus (CCB) and is also called the platform

clock. The frequency of the CCB is set using the following reset signals, as shown in Table 83:

•

SYSCLK input signal

•

Binary value on LA[28:31] at power up

Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note

that the DDR data rate is the determining factor in selecting the CCB bus frequency, since the CCB

frequency must equal the DDR data rate.

For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.

Table 81. DDR/DDR2 Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800, 1000, 1333 MHz

Min

Max

DDR/DDR2 Memory bus clock frequency

166

266

MHz

1, 2

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the

resulting SYSCLK frequency, e500 core frequency, and CCB clock frequency do not exceed their respective maximum

or minimum operating frequencies.

2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the platform clock frequency.

Table 82. Local Bus Clocking Specifications

Characteristic

Maximum Processor Core Frequency

Unit

Notes

800, 1000, 1333 MHz

Min

Max

Local bus clock speed (for Local Bus Controller)

166

MHz

Notes:

1. The Local bus clock speed on LCLK[0:2] is determined by CCB clock divided by the Local Bus PLL ratio programmed

in LCCR[CLKDIV]. See the reference manual for more information on this.

Table 83. CCB Clock Ratio

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

0000

16:1

1000

8:1

0001

Reserved

1001

9:1

0010

2:1

1010

10:1

0011

3:1

1011

Reserved

0100

4:1

1100

12:1

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