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PPC8567ECVTANJGA 数据表(PDF) 124 Page - Freescale Semiconductor, Inc |
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PPC8567ECVTANJGA 数据表(HTML) 124 Page - Freescale Semiconductor, Inc |
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124 / 139 page ![]() MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 124 Freescale Semiconductor Clocking 23.5 Frequency Options 23.5.1 SYSCLK to Platform Frequency Options Table 86 shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in comparison to the memory bus clock speed. 0_1000 8 1_1000 24 0_1001 9 1_1001 25 0_1010 10 1_1010 26 0_1011 11 1_1011 27 0_1100 12 1_1100 28 0_1101 13 1_1101 29 0_1110 14 1_1110 30 0_1111 15 1_1111 31 Table 86. Frequency Options of SYSCLK with Respect to Memory Bus Speeds CCB clock to SYSCLK Ratio SYSCLK (MHz) 16.66 25 33.33 41.66 66.66 83 100 111 133.33 166 Platform /CCB clock Frequency (MHz) 2 333 3 333 400 500 4 333 400 445 533 5 333 415 500 6 400 500 8 333 533 9 375 10 333 417 12 400 500 16 400 533 20 333 500 Table 85. QE Clock Multiplier cfg_ce_pll[0:4] (continued) Binary Value of PA[0:4] Signals cfg_ce_pll[0:4] Binary Value of PA[0:4] Signals cfg_ce_pll[0:4] |
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