PPC8567ECVTANJGA datasheet(123/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

123

Clocking

23.3

e500 Core PLL Ratio

Table 84 describes the clock ratio between the e500 core complex bus (CCB)platform and the e500 core

clock. This ratio is determined by the binary value of LBCTL, LALE and LGPL2 at power up, as shown

in Table 84.

23.4

QE/SYSCLK PLL Ratio

The QE clock is defined by a multiplier and divisor applied to the SYSCLK input signal, as shown in the

following equation:

QE clock = SYSCLK * cfg_ce_pll[0:4].

The multiplier and divisor is determined by the binary value of PA[0:4] at power up.

0101

5:1

1101

20:1

0110

6:1

1110

Reserved

0111

Reserved

1111

Reserved

Table 84. e500 Core to CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core:CCB Clock Ratio

Binary Value of

LBCTL, LALE,

LGPL2 Signals

e500 core:CCB Clock Ratio

000

4:1

100

2:1

001

9:2

101

5:2

010

Reserved

110

3:1

011

3:2

111

7:2

Table 85. QE Clock Multiplier cfg_ce_pll[0:4]

Binary Value of

PA[0:4] Signals

cfg_ce_pll[0:4]

Binary Value of

PA[0:4] Signals

cfg_ce_pll[0:4]

0_0000

1_0000

0_0001

Reserved

1_0001

0_0010

1_0010

0_0011

1_0011

0_0100

1_0100

0_0101

1_0101

0_0110

1_0110

0_0111

1_0111

Table 83. CCB Clock Ratio (continued)

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

Binary Value of

LA[28:31] Signals

CCB:SYSCLK Ratio

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