MPC8572ECLPXARLD datasheet(7/140 Pages) FREESCALE

7 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

– Up to 16 exact-match MAC addresses supported

– Broadcast address (accept/reject)

– Hash table match on up to 512 multicast addresses

– Promiscuous mode

— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

— RMON statistics support

— 10-Kbyte internal transmit and 2-Kbyte receive FIFOs

— Two MII management interfaces for control and status

— Ability to force allocation of header information and buffer descriptors into L2 cache

•

10/100 Fast Ethernet controller (FEC) management interface

— 10/100 Mbps full and half-duplex IEEE 802.3 MII for system management

— Note: When enabled, the FEC occupies eTSEC3 and eTSEC4 parallel interface signals. In such

a mode, eTSEC3 and eTSEC4 are only available through SGMII interfaces.

•

OCeaN switch fabric

— Full crossbar packet switch

— Reorders packets from a source based on priorities

— Reorders packets to bypass blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

•

Two integrated DMA controllers

— Four DMA channels per controller

— All channels accessible by the local masters

— Extended DMA functions (advanced chaining and striding capability)

— Misaligned transfer capability

— Interrupt on completed segment, link, list, and error

— Supports transfers to or from any local memory or I/O port

— Selectable hardware-enforced coherency (snoop/no snoop)

— Ability to start and flow control up to 4 (both Channel 0 and 1 for each DMA Controller) of the

8 total DMA channels from external 3-pin interface by the remote masters

— The Channel 2 of DMA Controller 2 is only allowed to initiate and start a DMA transfer by the

remote master, because only one of the 3-external pins (DMA2_DREQ[2]) is made available

— Ability to launch DMA from single write transaction

•

Serial RapidIO interface unit

— Supports RapidIO Interconnect Specification, Revision 1.2

— Both 1x and 4x LP-serial link interfaces

— Long- and short-haul electricals with selectable pre-compensation

— Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane

MPC8572ECLPXARLD 数据表(PDF) 7 Page - Freescale Semiconductor, Inc

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