MPC8572ECLPXARLD datasheet(13/140 Pages) FREESCALE

13 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8572E.

Figure 2. Overshoot/Undershoot Voltage for TVDD/BVDD/GVDD/LVDD/OVDD

The core voltage must always be provided at nominal 1.1 V. (See Table 2 for actual recommended core

voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must

be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the

associated I/O supply voltage. TVDD, BVDD, OVDD and LVDD based receivers are simple CMOS I/O

circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface

uses differential receivers referenced by the externally supplied MVREFn signal (nominally set to GVDD/2)

as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for

DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must

be properly driven and cannot be grounded.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

T/B/G/L/OVDD + 20%

T/B/G/L/OVDD

T/B/G/L/OVDD + 5%

of tCLOCK1

tCLOCK refers to the clock period associated with the respective interface:

VIH

VIL

Note:

For I2C and JTAG, tCLOCK references SYSCLK.

For DDR, tCLOCK references MCLK.

For eTSEC, tCLOCK references EC_GTX_CLK125.

For eLBC, tCLOCK references LCLK.

MPC8572ECLPXARLD 数据表(PDF) 13 Page - Freescale Semiconductor, Inc