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MPC8572ECLPXARLD 数据表(PDF) 109 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXARLD 数据表(HTML) 109 Page - Freescale Semiconductor, Inc |
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109 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 109 Package Description SD1_TX[6] PCIe1 Tx Data Lane 6 / SRIO or PCIe2 Tx Data Lane 2 / PCIe3 TX Data Lane 0 L24 O XVDD_SR DS1 — SD1_TX[5] PCIe1 Tx Data Lane 5 / SRIO or PCIe2 Tx Data Lane 1 K26 O XVDD_SR DS1 — SD1_TX[4] PCIe1 Tx Data Lane 4 / SRIO or PCIe2 Tx Data Lane 0 J24 O XVDD_SR DS1 — SD1_TX[3] PCIe1 Tx Data Lane 3 G24 O XVDD_SR DS1 — SD1_TX[2] PCIe1 Tx Data Lane 2 F26 O XVDD_SR DS1 — SD1_TX[1] PCIe1 Tx Data Lane 1] E24 O XVDD_SR DS1 — SD1_TX[0] PCIe1 Tx Data Lane 0 D26 O XVDD_SR DS1 — SD1_TX[7:0] Transmit Data (negative) M27, L25, K27, J25, G25, F27, E25, D27 OXVDD_SR DS1 — SD1_PLL_TPD PLL Test Point Digital J32 O XVDD_SR DS1 17 SD1_REF_CLK PLL Reference Clock H32 I XVDD_SR DS1 — SD1_REF_CLK PLL Reference Clock Complement H31 I XVDD_SR DS1 — Reserved — C29, K32 — — 26 Reserved — C30, K31 — — 27 Reserved — C24, C25, H26, H27 — — 28 Reserved — AL20, AL21 — — 29 SerDes (x4) SGMII SD2_RX[3:0] Receive Data (positive) AK32, AJ30, AF30, AE32 IXVDD_SR DS2 — SD2_RX[3:0] Receive Data (negative) AK31, AJ29, AF29, AE31 IXVDD_SR DS2 — SD2_TX[3] SGMII Tx Data eTSEC4 AH26 O XVDD_SR DS2 — SD2_TX[2] SGMII Tx Data eTSEC3 AG24 O XVDD_SR DS2 — SD2_TX[1] SGMII Tx Data eTSEC2 AE24 O XVDD_SR DS2 — Table 75. MPC8572E Pinout Listing (continued) Signal Signal Name Package Pin Number Pin Type Power Supply Notes |
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