MSC8252 datasheet(25/68 Pages) FREESCALE

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Electrical Characteristics

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

2.4

CLKIN Requirements

Table 5 summarizes the required characteristics for the CLKIN signal.

2.5

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8252.

2.5.1

DDR SDRAM DC Electrical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8252.

Note:

DDR2 SDRAM uses VDDDDR(typ) = 1.8 V and DDR3 SDRAM uses VDDDDR(typ) = 1.5 V.

2.5.1.1

DDR2 (1.8 V) SDRAM DC Electrical Characteristics

Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM.

Note:

At recommended operating conditions (see Table 3) with VDDDDR =1.8 V.

Table 5. CLKIN Requirements

Parameter/Condition1

Symbol

Min

Typ

Max

Unit

Notes

CLKIN duty cycle

—

CLKIN slew rate

—

V/ns

CLKIN peak period jitter

—

±150

—

CLKIN jitter phase noise at –56 dBc

—

500

KHz

AC input swing limits

ΔVAC

1.5

—

Input capacitance

CIN

——

—

Notes:

For clock frequencies, see the Clock chapter in the MSC8252 Reference Manual.

Measured at the rising edge and/or the falling edge at VDDIO/2.

Slew rate as measured from ±20% to 80% of voltage swing at clock input.

Phase noise is calculated as FFT of TIE jitter.

Table 6. DDR2 SDRAM Interface DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O reference voltage

MVREF

0.49

× VDDDDR

0.51

× VDDDDR

V2, 3, 4

Input high voltage

VIH

MVREF + 0.125

VDDDDR +0.3

Input low voltage

VIL

–0.3

MVREF – 0.125

I/O leakage current

IOZ

–50

μA6

Output high current (VOUT (VOH) = 1.37 V)

IOH

–13.4

—

Output low current (VOUT (VOL) = 0.33 V)

IOL

13.4

—

Notes:

VDDDDR is expected to be within 50 mV of the DRAM VDD supply voltage at all times. The DRAM and memory controller can

use the same or different sources.

MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal

to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations in the

DC-level of MVREF.

The voltage regulator for MVREF must be able to supply up to 300 μA.

Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.

Output leakage is measured with all outputs are disabled, 0 V

≤ V

OUT

≤ V

DDDDR.

Refer to the IBIS model for the complete output IV curve characteristics.

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