MSC8252 datasheet(46/68 Pages) FREESCALE

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MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor

Figure 21 shows the TDM transmit signal timing.

Figure 22 provides the AC test load for the TDM/SI.

2.6.4

Timers AC Timing Specifications

Table 32 lists the timer input AC timing specifications.

Note:

For recommended operating conditions, see Table 3.

Figure 23 shows the AC test load for the timers.

Figure 21. TDM Transmit Signals

Figure 22. TDM AC Test Load

Table 32. Timers Input AC Timing Specifications

Characteristics

Symbol

Minimum

Unit

Notes

Timers inputs—minimum pulse width

TTIWID

8ns

1, 2

Notes:

The maximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately.

Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any

external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.

Figure 23. Timer AC Test Load

TDMxTCK

TDMxTD

TDMxRCK

TDMxTFS (output)

TDMxTFS (input)

tDM

tDM_HIGH

tDM_LOW

tDMIVKH

tDM_OUTAC

tDMFSIXKH

tDMTKHOV

tDMTKHOX

tDM_OUTHI

tDMFSKHOV

tDMFSKHOX

Output

Z0 = 50 Ω

VDDIO/2

RL = 50 Ω

Output

Z0 = 50 Ω

VDDIO/2

RL = 50 Ω

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