MSC8252 datasheet(65/68 Pages) FREESCALE

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Product Documentation

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

Product Documentation

Following is a general list of supporting documentation:

•

MSC8252 Technical Data Sheet (MSC8252). Details the signals, AC/DC characteristics, clock signal characteristics,

package and pinout, and electrical design considerations of the MSC8252 device.

•

MSC8252 Reference Manual (MSC8252RM). Includes functional descriptions of the extended cores and all the

internal subsystems including configuration and programming information.

•

Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8252 device.

•

QUICC Engine Block Reference Manual with Protocol Interworking (QEIWRM). Provides detailed information

regarding the QUICC Engine technology including functional description, registers, and programming information.

•

SC3850 DSP Core Reference Manual. Covers the SC3850 core architecture, control registers, clock registers, program

control, and instruction set.

•

MSC8156SC3850 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and

registers.

Revision History

Table 50 provides a revision history for this data sheet.

Table 50. Document Revision History

Rev.

Date

Description

Apr. 2010

• Initial public release.

May 2010

• Changed connection for pins K17, L14, L16, M15, M17, and N14 from VDD to VSS in Table 1.

• Updated Section 3.1.2, Power-On Ramp Time.

Jun 2010

• Changed the number of cores in the first bullet on the first page from four to two.

• The correction to the L16 connection was not made in Rev. 1. Fixed the entry to change from VDD to VSS in

Table 1.

Dec 2010

• Updated Table 16.

• Updated Section 3.1.2, Power-On Ramp Time.

• Updated Section 4, Ordering Information.

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