MSC8252 datasheet(39/68 Pages) FREESCALE

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Electrical Characteristics

MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Freescale Semiconductor

Figure 13 shows the DDR SDRAM output timing diagram.

Figure 14 provides the AC test load for the DDR2 and DDR3 controller bus.

2.6.1.3

DDR2 and DDR3 SDRAM Differential Timing Specifications

This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM controller interface.

Figure 15 shows the differential timing specification.

Note:

VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as

MCK or MDQS).

Figure 13. DDR SDRAM Output Timing

Figure 14. DDR2 and DDR3 Controller Bus AC Test Load

Figure 15. DDR2 and DDR3 SDRAM Differential Timing Specifications

ADDR/CMD

tDDKHAS, tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

tMCK

tDDKLDX

tDDKHDX

tDDKHAX ,tDDKHCX

Write A0

NOOP

tDDKHME

tDDKHMP

Output

Z0 = 50 Ω

RL = 50 Ω

VDDDDR/2

VTR

VCP

GND

GVDD

VOX or VIX

GVDD/2

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