Data Sheet TLE 6232 GP

V2.3

Page

2009-11-18

9

SPI Signal Description

CS - Chip Select. The system microcontroller selects the TLE 6232 GP by means of the CS

pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice

versa.

CS High to Low transition: - diagnostic status information is transferred from the power

outputs into the shift register.

- serial input data can be clocked in from then on

- SO changes from high impedance state to logic high or low

state corresponding to the SO bits

CS Low to High transition: - transfer of SI bits from shift register into output buffers

- reset of diagnosis register

To avoid any false clocking the serial clock input pin SCLK should be logic low state during

high to low transition of

CS . When CS is in a logic high state, any signals at the SCLK and

SI pins are ignored and SO is forced into a high impedance state.

SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE

6232 GP. The serial input (SI) accepts data into the input shift register on the falling edge of

SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the

rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever

chip select

CS makes any transition. The number of clock pulses will be counted during a

chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were

counted during

CS is active.

SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-

mation is read in on the falling edge of SCLK. Input data is latched in the shift register and

then transferred to the control buffer of the output stages.

The input data consists of two bytes - a "control byte” followed by a "data byte". The control

byte contains the information as to whether the data byte will be accepted or ignored (see di-

agnostics section). The data byte contains the input information for the six channels. A logic

high level at this pin (within the data byte) will switch on the power switch, provided that the

corresponding parallel input is also switched on (AND-operation for channel 1 to 6).

SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant

bit first. SO is in a high impedance state until the

CS pin goes to a logic low state. New diag-

nostic data will appear at the SO pin following the rising edge of SCLK.

RESET

- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and

switches all outputs OFF. An internal pull-up structure is provided on chip.

In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing

from1“ and „0“ the data output SO remains into tri-state.