STM8L15 datasheet(57/122 Pages) STMICROELECTRONICS

57 / 122 page

STM8L151xx, STM8L152xx

Option bytes

Doc ID 15962 Rev 5

57/122

Table 12.

Option byte description

Option

byte

No.

Option description

OPT0

ROP[7:0] Memory readout protection (ROP)

0xAA: Disable readout protection (write access via SWIM protocol)

Refer to Readout protection section in the STM8L15x reference manual (RM0031).

OPT1

UBC[7:0] Size of the user boot code area

0x00: no UBC

0x01: the UBC contains only the interrupt vectors.

0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt

vectors.

0x03 - Page 0 to 2 reserved for UBC, memory write-protected

≥ 0xFE - Page 0 to 254 reserved for UBC, memory write-protected

Refer to User boot code section in the STM8L15x reference manual (RM0031).

OPT2

Reserved

OPT3

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

WWDG_HW: Window watchdog

0: Window watchdog activated by software

1: Window watchdog activated by hardware

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode

1: Window watchdog generates a reset when MCU enters Halt mode

OPT4

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

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