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STM8L15 数据表(PDF) 35 Page - STMicroelectronics |
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STM8L15 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 122 page ![]() STM8L151xx, STM8L152xx Memory and register map Doc ID 15962 Rev 5 35/122 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 9. Figure 9. Memory map 1. Table 6 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. The VREFINT_Factory_CONV byte represents the LSB of the VREFINT 12-bit ADC conversion result. The MSB have a fixed value: 0x6. 3. The TS_Factory_CONV_V90 byte represents the LSB of the V90 12-bit ADC conversion result. The MSB have a fixed value: 0x3. 4. Refer to Table 8 for an overview of hardware register mapping, to Table 7 for details on I/O port hardware registers, and to Table 9 for information on CPU/SWIM/debug module controller registers. GPIO and peripheral registers 0x00 0000 Reserved Medium-density (up to 32 Kbytes) Reset and interrupt vectors 0x00 1000 0x00 13FF RAM 0x00 07FF (2 Kbytes) (1) (513 bytes) (1) 0x00 1400 Data EEPROM 0x00 4800 0x00 48FF 0x00 4900 0x00 7FFF 0x00 8000 0x00 FFFF 0x00 0800 0x00 0FFF 0x00 47FF 0x00 7EFF 0x00 8080 0x00 807F 0x00 7F00 Reserved Reserved including Stack (1 Kbyte) Option bytes 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 Reserved 0x00 5FFF Boot ROM 0x00 6000 0x00 67FF (2 Kbytes) 0x00 6800 Reserved CPU/SWIM/Debug/ITC Registers 0x00 5000 GPIO Ports 0x00 5050 Flash 0x00 50C0 ITC-EXTI 0x00 50D3 RST 0x00 50E0 CLK 0x00 50F3 WWDG 0x00 5210 IWDG 0x00 5230 BEEP 0x00 5250 RTC 0x00 5280 SPI1 0x00 52B0 I2C1 0x00 52E0 USART1 TIM2 TIM3 TIM1 TIM4 IRTIM ADC1 0x00 5070 DMA1 SYSCFG DAC LCD RI 0x00 509E 0x00 50A0 0x00 50B0 0x00 5140 0x00 5200 0x00 52FF 0x00 5340 0x00 5380 0x00 5400 0x00 5430 0x00 5440 COMP Flash program memory WFE 0x00 50A6 0x00 50B2 PWR 0x00 4910 0x00 4911 0x00 4926 0x00 4925 0x00 4931 0x00 4932 0x00 4909 VREFINT_Factory_CONV(2) TS_Factory_CONV_V90(3) 0x00 4912 Reserved Unique ID Reserved |
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