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MIC3003GML 数据表(PDF) 57 Page - Micrel Semiconductor

部件名 MIC3003GML
功能描述  FOM Management IC with Internal Calibration
PDF  75 Pages
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制造商  MICREL [Micrel Semiconductor]
网页  http://www.micrel.com
标志 MICREL - Micrel Semiconductor

MIC3003GML 数据表(HTML) 57 Page - Micrel Semiconductor

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Micrel, Inc.
MIC3003
November 2009
57
M9999-111209-C
hbwhelp@micrel.com or (408) 955-1690
OEM Configuration Register 1 (OEMCFG1)
D[7]
INV
read/write
D[6]
GAIN
read/write
D[5]
BIASREF
read/write
D[4]
RFB[2]
read/write
D[3]
RFB[1]
read/write
D[2]
RFB[0]
read/write
D[1]
SRCE
read/write
D[0]
SPOL
read/write
Default value
0000 0010b = 02h
Serial address
A6h
Byte address
1 = 01h
A write to OEMCFG1 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a
new conversion sequence once the write operation is complete.
All bits in OEMCFG1 are non-volatile and will be maintained through power and reset cycles. A valid OEM password is
required for access to this register.
Bit(s)
Function
Operation
D[7]
INV
Inverts the APC op-amp inputs.
When low, the BIAS DAC output is
connected to the “+”input and FB is
connected to the “–” input of the op
amp. Set low to use the APC
feedback loop.
0 = emitter follower (no inversion);
1 = common emitter (inverted); read/write; non-volatile.
D[6]
GAIN
Sets the feedback voltage range by
changing the APCDAC output
swing; 0-V
REF for optical feedback,
0-V
REF/4 for electrical feedback.
1 = VREF/4 full scale;
0 = VREF full scale
D[5]
BIASREF
Selects whether FB and VMPD are
referenced to ground or V
DD and
selects feedback resistor termination
voltage (V
DDA or GNDA).
1 = VDD; 0 = GNDA
If this bit is set to 0, bit 1 should be set to 1
If this bit is set to 1, bit 1 should be set to 0
D[4:2]
RFB[2:0]
Selects internal feedback resistance.
Resistors will be terminated to VDDA
or GNDA according to BIASREF.
000 = ∞
001 = 800 Ω
010 = 1.6kΩ
011 = 3.2kΩ
100 = 6.4kΩ
101 = 12.8kΩ
110 = 25.6kΩ
111 = 51.2kΩ
D[1]
SRCE
V
BIAS source or sink drive.
1 = source (NPN): bit 5 should be set to 0.
0 = sink (PNP): bit 5 should be set to 1.
D[0]
SPOL
Polarity of the shutdown output,
SHDN, when active.
1 = SHDN is active-high
0 = SHDN is active-low



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