MIC3003GML datasheet(13/75 Pages) MICREL

13 / 75 page

Micrel, Inc.

MIC3003

November 2009

M9999-111209-C

hbwhelp@micrel.com or (408) 955-1690

Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Control and Status I/O Timing, TXFAULT, TXDISABLE, RS0, RRSOUT, and RXLOS

tOFF

TXDISABLE Assert Time

From input asserted to optical output

at 10% of nominal, CCOMP = 10nF.

µs

tON

TXDISABLE De-assert Time

From input de-asserted to optical output

at 90% of nominal, CCOMP = 10nF.

tINIT

Initialization Time

From power on or transmitter enabled to

optical output at 90% of nominal and

TX_FAULT de-asserted. Note 10

300

tINIT2

Power-on Initialization Time

From power on to APC loop-enabled.

200

tFAULT

TXFAULT Assert Time

From fault condition to TXFAULT

assertion. Note 10

µs

tRESET

Fault Reset Time

Length of time TXDISABLE must be

asserted to reset fault condition.

µs

tLOSS_ON

RXLOS Assert Time

From loss of signal to RXLOS asserted.

µs

tLOSS_OFF

RXLOS De-assert Time

From signal acquisition to LOS

de-asserted.

100

µs

tDATA

Analog Parameter Data Ready

From power on to valid analog

parameter data available. Note 10

400

tPROP_IN

TXFAULT, TXDISABLE, RXLOS,

RS0, RS1 Input Propagation Time

Time from input change to

corresponding internal register bit set or

cleared. Note 10

µs

tPROP_OUT TXFAULT, TRSOUT, TRRSOUT,

/INT, QGPO Output Propagation

Time

From an internal register bit set or

cleared to corresponding output change.

Note 10

µs

Fault Comparators

FLTTMR

Fault Suppression Timer Clock

Period

Note 10

0.475

0.5

0.525

Accuracy

-3

%/fs

tREJECT

Glitch Rejection

Maximum length pulse that will not

cause output to change state. Note 10

4.5

µs

High level

%VDDA

VSAT

Saturation Detection Threshold

Low level

%VDDA

Power-On Hour Meter

Timebase Accuracy

0°C ≤ TA ≤ +70°, Note 10

-5

–40°C ≤ TA ≤ +105°C

+10

-10

Resolution

Note 10

hours

Non-Volatile (FLASH) Memory

tWR

Write Cycle Time, Note 11

Measured from the SMBus STOP

condition of a one-byte to eight-byte

write transaction. Note 10

NVRAM Data Retention

100

years

Endurance

Maximum permitted number of write

cycles to any single NVRAM location

10,000

cycles

Notes:

10. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.

11. The MIC3003 will not respond to serial bus transactions during an EEPROM write cycle. The host will receive a NACK response during tWR.

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