R5F364AMNFB datasheet(42/92 Pages) RENESAS

42 / 92 page

R01DS0032EJ0200 Rev.2.00

Page 42 of 88

Feb 07, 2011

M16C/64A Group

5. Electrical Characteristics

Note:

The average output current is the mean value within 100 ms.

Note:

The device is operationally guaranteed under these operating conditions.

Figure 5.1

Ripple Waveform

Table 5.3

Recommended Operating Conditions (2/3)

VCC1 = VCC2 = 2.7 to 5.5 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.

Symbol

Parameter

Standard

Unit

Min.

Typ.

Max.

IOL(sum) Low peak

output

current

Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7

80.0

IOL(peak) Low peak

output

current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

10.0

IOL(avg)

Low

average

output

current (1)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7

5.0

f(XIN)

Main clock input

oscillation frequency

VCC1 = 2.7 V to 5.5 V

MHz

f(XCIN)

Sub clock oscillation frequency

32.768

kHz

f(PLL)

PLL clock oscillation

frequency

VCC1 = 2.7 V to 5.5 V

MHz

f(BCLK)

CPU operation clock

MHz

tSU(PLL) PLL frequency

synthesizer

stabilization wait time

VCC1 = 5.0 V

VCC1 = 3.0 V

Table 5.4

Recommended Operating Conditions (3/3) (1)

VCC1 = 2.7 to 5.5 V, VSS = 0 V, and Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.

The ripple voltage must not exceed Vr(VCC1) and/or dVr(VCC1)/dt.

Symbol

Parameter

Standard

Unit

Min.

Typ.

Max.

Vr(VCC1)

Allowable ripple voltage

VCC1 = 5.0 V

0.5

Vp-p

VCC1 = 3.0 V

0.3

Vp-p

dVr(VCC1)/dt Ripple voltage falling gradient

VCC1 = 5.0 V

0.3

V/ms

VCC1 = 3.0 V

0.3

V/ms

Vr(

)

VCC1

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