R5F364AMNFB datasheet(86/92 Pages) RENESAS

86 / 92 page

R01DS0032EJ0200 Rev.2.00

Page 86 of 88

Feb 07, 2011

M16C/64A Group

5. Electrical Characteristics

VCC1 = VCC2 = 3 V

Switching Characteristics

(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)

5.3.4.3

In 2 or 3 Waits Setting, and When Accessing External Area and Using

Multiplexed Bus

Notes:

Calculated according to the BCLK frequency as follows:

n is 2 for 2 waits setting, 3 for 3 waits setting.

Calculated according to the BCLK frequency as follows:

When using multiplexed bus, set f(BCLK) 12.5 MHz or less.

Table 5.57

Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When

Accessing External Area and Using Multiplexed Bus) (5)

Symbol

Parameter

Measuring

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See

Figure 5.27

th(BCLK-AD)

Address output hold time (in relation to BCLK)

0ns

th(RD-AD)

Address output hold time (in relation to RD)

(Note 1)

th(WR-AD)

Address output hold time (in relation to WR)

(Note 1)

td(BCLK-CS)

Chip select output delay time

th(BCLK-CS)

Chip select output hold time (in relation to BCLK)

0ns

th(RD-CS)

Chip select output hold time (in relation to RD)

(Note 1)

th(WR-CS)

Chip select output hold time (in relation to WR)

(Note 1)

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

0ns

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

0ns

td(BCLK-DB)

Data output delay time (in relation to BCLK)

th(BCLK-DB)

Data output hold time (in relation to BCLK)

0ns

td(DB-WR)

Data output delay time (in relation to WR)

(Note 2)

th(WR-DB)

Data output hold time (in relation to WR)

(Note 1)

td(BCLK-ALE)

ALE signal output delay time (in relation to BCLK)

th(BCLK-ALE)

ALE signal output hold time (in relation to BCLK)

−4ns

td(AD-ALE)

ALE signal output delay time (in relation to Address)

(Note 3)

th(AD-ALE)

ALE signal output hold time (in relation to Address)

(Note 4)

td(AD-RD)

RD signal output delay from the end of address

0ns

td(AD-WR)

WR signal output delay from the end of address

0ns

tdz(RD-AD)

Address output floating start time

8ns

0.5

BCLK

()

----------------------10 ns

[]

–

0.5

–

() 10

BCLK

()

------------------------------------50 ns

[]

–

0.5

BCLK

()

----------------------40 ns

[]

–

0.5

BCLK

()

----------------------15 ns

[]

–

R5F364AMNFB 数据表(PDF) 86 Page - Renesas Technology Corp

R5F364AMNFB 数据表(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载

链接网址

R5F364AMNFB 数据表(PDF) 86 Page - Renesas Technology Corp

R5F364AMNFB 数据表(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表 下载

链接网址

数据表下载