CC2500-RTR1 datasheet(32/96 Pages) TI

32 / 96 page

CC2500

SWRS040C

Page 32 of 89

options. Refer also to the

CC2500 Errata Notes

[1].

15.4.1 PKTCTRL0.CC2400_EN=0

If PKTCTRL0.CC2400_EN=0 it is possible to

read back the CRC status in 2 different ways:

1) Set PKTCTRL1.APPEND_STATUS=1 and

read the CRC_OK flag in the MSB of the

second byte appended to the RX FIFO after

the packet data. This requires double buffering

of the packet, i.e. the entire packet content of

the RX FIFO must be completely read out

before it is possible to check whether the CRC

indication is OK or not.

2) To avoid reading the entire RX FIFO,

another

solution

use

the

PKTCTRL1.CRC_AUTOFLUSH

feature. If this

feature is enabled, the entire RX FIFO will be

flushed

the

CRC

check

fails.

GDOx_CFG

=0x06 the GDOx pin will be asserted

when a sync word is found. The GDOx pin will

be de-asserted at the end of the packet. When

the latter occurs the MCU should read the

number of bytes in the RX FIFO from the

RXBYTES.NUM_RXBYTES

status register. If

RXBYTES.NUM_RXBYTES

=0 the CRC check

failed

and

the

FIFO

flushed.

RXBYTES.NUM_RXBYTES

>0 the CRC check

was OK and data can be read out of the FIFO.

15.4.2 PKTCTRL0.CC2400_EN=1

If PKTCTRL0.CC2400_EN=1 the CRC can be

checked as outlined in 1) in Section 15.4.1 as

well as by reading the CRC_OK flag available

in the PKTSTATUS[7] register, in the LQI[7]

status register or from one of the GDO pins if

GDOx_CFG

is 0x07 or 0x15.

The PKTCTRL1.CRC_AUTOFLUSH

or data

whitening

cannot

used

when

PKTCTRL0.CC2400_EN

=1.

15.5

Packet Handling in Transmit Mode

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

length is enabled. The length byte has a value

equal to the payload of the packet (including

the

optional

address

byte).

address

recognition is enabled on the receiver, the

second byte written to the TX FIFO must be

the address byte. If fixed packet length is

enabled, then the first byte written to the TX

FIFO should be the address (if the receiver

uses address recognition).

The modulator will first send the programmed

number of preamble bytes. If data is available

in the TX FIFO, the modulator will send the

two-byte (optionally 4-byte) sync word and

then the payload in the TX FIFO. If CRC is

enabled, the checksum is calculated over all

the data pulled from the TX FIFO and the

result is sent as two extra bytes following the

payload data. If the TX FIFO runs empty

before

the

complete

packet

has

been

transmitted,

the

radio

will

enter

TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed

will not restart TX mode.

If whitening is enabled, everything following

the sync words will be whitened. This is done

before the optional FEC/Interleaver stage.

Whitening

enabled

setting

PKTCTRL0.WHITE_DATA

=1.

If FEC/Interleaving is enabled, everything

following the sync words will be scrambled by

the interleaver and FEC encoded before being

modulated.

FEC

enabled

setting

MDMCFG1.FEC_EN

=1.

15.6

Packet Handling in Receive Mode

In receive mode, the demodulator and packet

handler will search for a valid preamble and

the sync word. When found, the demodulator

has obtained both bit and byte synchronism

and will receive the first payload byte.

FEC/Interleaving

enabled,

the

FEC

decoder will start to decode the first payload

byte. The interleaver will de-scramble the bits

before any other processing is done to the

data.

If whitening is enabled, the data will be de-

whitened at this stage.

When variable packet length mode is enabled,

the first byte is the length byte. The packet

handler stores this value as the packet length

and receives the number of bytes indicated by

the length byte. If fixed packet length mode is

used, the packet handler will accept the

programmed number of bytes.

Next, the packet handler optionally checks the

address and only continues the reception if the

address matches. If automatic CRC check is

enabled, the packet handler computes CRC

and matches it with the appended CRC

checksum.

At the end of the payload, the packet handler

will optionally write two extra packet status

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