CC2500-RTR1 datasheet(44/96 Pages) TI

44 / 96 page

CC2500

SWRS040C

Page 44 of 89

1. Read

RXBYTES.NUM_RXBYTES

repeatedly at a rate guaranteed to be at

least twice that of which RF bytes are

received until the same value is returned

twice; store value in

If n < # of bytes remaining in packet, read

n-1 bytes from the RX FIFO.

Repeat steps 1 and 2 until n = # of bytes

remaining in the packet.

Read the remaining bytes from the RX

FIFO.

The 4-bit FIFOTHR.FIFO_THR setting is used

to program threshold points in the FIFOs.

Table 29 lists the 16 FIFO_THR settings and

the corresponding thresholds for the RX and

TX FIFOs. The threshold value is coded in

opposite directions for the RX FIFO and TX

FIFO. This gives equal margin to the overflow

and underflow conditions when the threshold

is reached.

A signal will assert when the number of bytes

in the FIFO is equal to or higher than the

programmed threshold. The signal can be

viewed on the GDO pins (see Section 28 on

page 51).

Figure 20 shows the number of bytes in both

the RX FIFO and TX FIFO when the threshold

flag toggles, in the case of FIFO_THR=13.

Figure 19 shows the signal as the respective

FIFO is filled above the threshold, and then

drained below.

53 54 55 56

NUM_RXBYTES

GDO

NUM_TXBYTES

GDO

Figure 19: FIFO_THR=13 vs. Number of

Bytes in FIFO (GDOx_CFG=0x00 in RX and

GDOx_CFG

=0x02 in TX)

FIFO_THR

Bytes in TX FIFO

Bytes in RX FIFO

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Table 29: FIFO_THR Settings and the

Corresponding FIFO Thresholds

56 bytes

8 bytes

Overflow

margin

Underflow

margin

FIFO_THR=13

RXFIFO

TXFIFO

Figure 20: Example of FIFOs at Threshold

21 Frequency Programming

The frequency programming in

CC2500 is

designed

minimize

the

programming

needed in a channel-oriented system.

To set up a system with channel numbers, the

desired channel spacing is programmed with

the

MDMCFG0.CHANSPC_M

and

MDMCFG1.CHANSPC_E

registers. The channel

spacing registers are mantissa and exponent

respectively.

The base or start frequency is set by the 24 bit

frequency word located in the FREQ2, FREQ1

and FREQ0 registers. This word will typically

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