CC2500-RTR1 datasheet(38/96 Pages) TI

38 / 96 page

CC2500

SWRS040C

Page 38 of 89

interference and time-varying signal strengths.

In order to increase the robustness to errors

spanning multiple bits, interleaving is used

when FEC is enabled. After de-interleaving, a

continuous span of errors in the received

stream will become single errors spread apart.

CC2500 employs matrix interleaving, which is

illustrated

Figure

14.

The

on-chip

interleaving and de-interleaving buffers are 4 x

4 matrices. In the transmitter, the data bits

from the rate ½ convolutional coder are written

into the rows of the matrix, whereas the bit

sequence to be transmitted is read from the

columns of the matrix. Conversely, in the

receiver, the received symbols are written into

the rows of the matrix, whereas the data

passed onto the convolutional decoder is read

from the columns of the matrix.

When FEC and interleaving is used at least

one

extra

byte

required

for

trellis

termination. In addition, the amount of data

transmitted over the air must be a multiple of

the size of the interleaver buffer (two bytes).

The

packet

control

hardware

therefore

automatically inserts one or two extra bytes at

the end of the packet, so that the total length

of the data to be interleaved is an even

number. Note that these extra bytes are

invisible to the user, as they are removed

before the received packet enters the RX

FIFO.

When FEC and interleaving is used the

minimum data payload is 2 bytes.

Packet

Engine

FEC

Encoder

Modulator

Interleaver

Write buffer

Interleaver

Read buffer

Demodulator

FEC

Decoder

Packet

Engine

Interleaver

Write buffer

Interleaver

Read buffer

Figure 14: General Principle of Matrix Interleaving

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