Stand-Alone, 10-Channel, 10-Bit System Monitors

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21

Channel Configuration Register

Each channel has a channel configuration register (Table

13) defining the number of consecutive faults to be

detected before setting the alarm bits and generating an

interrupt, as well as controlling the digital averaging func-

tion. At power-up and after a RESET command, the regis-

ter defaults to 00 hex (no averaging, alarm on first fault).

Fault Bits

The value stored in the fault bits (B7–B4) in the channel

configuration register sets the number of faults that

must occur for that channel before generating an inter-

rupt. Encoding of the fault bits is straight binary with

values 0 to 15. A fault occurs in a channel when the

value in its current data register is outside the range

defined by the channel’s upper and lower threshold

registers. For example, if the number of faults set by the

fault bits is N, an interrupt is generated when the num-

ber of consecutive faults (see following note) reach

(N + 1). The fault bits default to 0 hex at power-up.

Note: Consecutive faults are those happening in con-

secutive conversion scans for the same channel. If a

fault occurs and the next scan finds the input within the

normal range defined by the thresholds, the fault

counter resets. If the next counter finds the input signal

outside the opposite threshold, rather than the previous

one, the fault counter also resets. The fault counter

increments only when counting consecutive faults

exceeding the same threshold (Figure 4).

Averaging

The averaging calculated by the data-acquisition algo-

rithm of the MAX1153/MAX1154 improves the input sig-

nal-to-noise ratio (SNR) by reducing the signal

bandwidth digitally. The formula below describes the

filter implemented in the MAX1153/MAX1154:

current value = [(N - 1) / N] x past value +

[(present value) / N]

where N = number of samples indicated in Table 14.

The averaging bits (B3–B0) in the channel configuration

register can set the N factor to any value in Table 14.

The output of the filter-running algorithm is continuously

available in the current data register. The starting value

used by the algorithm is the initial state of the current

data register. The current data register is reset to mid-

scale (200 hex) at power-up or after a RESET com-

mand, but it can be loaded with a more appropriate

initial value to improve the filter settling time.

At power-up or after a RESET command, the B3–B0

bits of the channel configuration register are set to 0

hex, corresponding to a number of averaged N = 1, no

averaging. See Table 13 and the

Write-Selected

Channel Configuration Registers section for program-

ming details. See Table 14 for N encoding.

As in all digital filters, truncation can be a cause of sig-

nificant errors. In the MAX1153/MAX1154, 24 bits of

precision are maintained in the digital averaging func-

tions, maintaining a worst-case truncation error of well

below an LSB. The worst-case truncation error in the

MAX1153/MAX1154 is given by the following:

where N = number of conversions averaged.

Therefore, the worst truncation error when averaging

256 samples is 0.01557 LSBs.

worst case truncation error

N

LSBs

-

-

=

1

16384

Table 13. Channel Configuration Register Format

B7 (MSB)

B6

B5

B4

B3

B2

B1

B0 (LSB)

Fault B3

Fault B2

Fault B1

Fault B0

Ave B3

Ave B2

Ave B1

Ave B0

Table 14. Conversion Average Encoding

CODE

N

0000

1, no averaging

0001

2

0010

4

0011

8

0100

16

0101

32

0110

64

0111

128

1000

256

1001

512

1010

1024

1011

2048

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved