HT66F40 datasheet(49/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

Entering the SLEEP1 Mode

There is only one way for the device to enter the

SLEEP1 Mode and that is to execute the

²HALT²

instruction in the application program with the IDLEN bit

in SMOD register equal to

²0² and the WDT or LVD on.

When this instruction is executed under the conditions

described above, the following will occur:

· The system clock and Time Base clock will be

stopped and the application program will stop at the

²HALT² instruction, but the WDT or LVD will remain

with the clock source coming from the fSUB clock.

· The Data Memory contents and registers will maintain

their present condition.

· The WDT will be cleared and resume counting if the

WDT clock source is selected to come from the fSUB

clock as the WDT is enabled.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will

be set and the Watchdog time-out flag, TO, will be

cleared.

Entering the IDLE0 Mode

There is only one way for the device to enter the IDLE0

Mode and that is to execute the

²HALT² instruction in the

application program with the IDLEN bit in SMOD register

equal to

²1² and the FSYSON bit in WDTC register equal

²0². When this instruction is executed under the condi-

tions described above, the following will occur:

· The system clock will be stopped and the application

program will stop at the

²HALT² instruction, but the

Time Base clock and fSUB clock will be on.

· The Data Memory contents and registers will maintain

their present condition.

· The WDT will be cleared and resume counting if the

WDT clock source is selected to come from the fSUB

clock and the WDT is enabled. The WDT will stop if its

clock source originates from the system clock.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will

be set and the Watchdog time-out flag, TO, will be

cleared.

Entering the IDLE1 Mode

There is only one way for the device to enter the IDLE1

Mode and that is to execute the

²HALT² instruction in the

application program with the IDLEN bit in SMOD register

equal to

²1² and the FSYSON bit in WDTC register equal

²1². When this instruction is executed under the with

conditions described above, the following will occur:

· The system clock and Time Base clock and f

SUB clock

will be on and the application program will stop at the

²HALT² instruction.

· The Data Memory contents and registers will maintain

their present condition.

· The WDT will be cleared and resume counting if the

WDT is enabled regardless of the WDT clock source

which originates from the fSUB clock or from the system

clock.

· The I/O ports will maintain their present conditions.

· In the status register, the Power Down flag, PDF, will

be set and the Watchdog time-out flag, TO, will be

cleared.

Standby Current Considerations

As the main reason for entering the SLEEP or IDLE

Mode is to keep the current consumption of the device

to as low a value as possible, perhaps only in the order

of several micro-amps except in the IDLE1 Mode, there

are other considerations which must also be taken into

account by the circuit designer if the power consumption

is to be minimised. Special attention must be made to

the I/O pins on the device. All high-impedance input pins

must be connected to either a fixed high or low level as

any floating input pins could create internal oscillations

and result in increased current consumption. This also

applies to devices which have different package types,

as there may be unbonbed pins. These must either be

setup as outputs or if setup as inputs must have

pull-high resistors connected.

Care must also be taken with the loads, which are con-

nected to I/O pins, which are setup as outputs. These

should be placed in a condition in which minimum cur-

rent is drawn or connected only to external circuits that

do not draw current, such as other CMOS inputs. Also

note that additional standby current will also be required

if the configuration options have enabled the LXT or

LIRC oscillator.

In the IDLE1 Mode the system oscillator is on, if the sys-

tem oscillator is from the high speed system oscillator,

the additional standby current will also be perhaps in the

order of several hundred micro-amps

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