HT66F40 datasheet(97/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

tion within the TM is useful for applications which require

functions such as motor control, heating control, illumi-

nation control etc. By providing a signal of fixed fre-

quency but of varying duty cycle on the TM output pin, a

square wave AC waveform can be generated with vary-

ing equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform

can be controlled, the choice of generated waveform is

extremely flexible. In the PWM mode, the TnCCLR bit

has no effect on the PWM operation. Both of the CCRA

and CCRP registers are used to generate the PWM

waveform, one register is used to clear the internal

counter and thus control the PWM waveform frequency,

while the other one is used to control the duty cycle.

Which register is used to control either frequency or duty

cycle is determined using the TnDPX bit in the TMnC1

can therefore be controlled by the values in the CCRA

and CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP,

will be generated when a compare match occurs from

either Comparator A or Comparator P. The TnOC bit in

the TMnC1 register is used to select the required polar-

ity of the PWM waveform while the two TnIO1 and

TnIO0 bits are used to enable the PWM output or to

force the TM output pin to a fixed high or low level. The

TnPOL bit is used to reverse the polarity of the PWM

output waveform.

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRP

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRP

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 0

Note:

1. Here TnDPX=0 -- Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

HT66F40 数据表(PDF) 97 Page - Holtek Semiconductor Inc

HT66F40 数据表(HTML) 97 Page - Holtek Semiconductor Inc

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