HT66F40 datasheet(52/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

8 - s t a g e D i v i d e r

f S

W D T T i m e - o u t

( 2 8 / f S ~ 2 1 5 / f S )

f S / 2 8

W D T P r e s c a l e r

8 - t o - 1 M U X

C l e a r W D T T y p e

C o n f i g u r a t i o n O p t i o n

C L R W D T 1 F l a g

C L R W D T 2 F l a g

1 o r 2 I n s t r u c t i o n s

C L R

f S U B

W S 2 ~ W S 0

( f S / 2 8 ~ f S / 2 1 5 )

f S Y S / 4

L X T

L I R C

C o n f i g u r a t i o n

O p t i o n

C o n f i g u r a t i o n

O p t i o n

Watchdog Timer

Watchdog Timer Operation

The Watchdog Timer operates by providing a device re-

set when its timer overflows. This means that in the ap-

plication program and during normal operation the user

has to strategically clear the Watchdog Timer before it

overflows to prevent the Watchdog Timer from execut-

ing a reset. This is done using the clear watchdog in-

structions. If the program malfunctions for whatever

reason, jumps to an unkown location, or enters an end-

less loop, these clear instructions will not be executed in

the correct manner, in which case the Watchdog Timer

will overflow and reset the device. Some of the Watch-

dog Timer options, such as enable/disable, clock source

selection and clear instruction type are selected using

configuration options. In addition to a configuration op-

tion to enable/disable the Watchdog Timer, there are

also four bits, WDTEN3~WDTEN0, in the WDTC regis-

ter to offer an additional enable/disable control of the

Watchdog Timer. To disable the Watchdog Timer, as

well as the configuration option being set to disable, the

WDTEN3~WDTEN0 bits must also be set to a specific

value of

²1010². Any other values for these bits will keep

the Watchdog Timer enabled, irrespective of the configu-

ration enable/disable setting. After power on these bits

will have the value of 1010. If the Watchdog Timer is used

it is recommended that they are set to a value of 0101 for

maximum noise immunity. Note that if the Watchdog

Timer has been disabled, then any instruction relating to

its operation will result in no operation.

WDT Configuration

Option

WDTEN3~

WDTEN0 Bits

WDT

WDT Enable

xxxx

Enable

WDT Disable

Except 1010

Enable

WDT Disable

1010

Disable

Watchdog Timer Enable/Disable Control

Under normal program operation, a Watchdog Timer

time-out will initialise a device reset and set the status

bit TO. However, if the system is in the SLEEP or IDLE

Mode, when a Watchdog Timer time-out occurs, the TO

bit in the status register will be set and only the Program

Counter and Stack Pointer will be reset. Three methods

can be adopted to clear the contents of the Watchdog

Timer. The first is an external hardware reset, which

means a low level on the RES pin, the second is using

the Watchdog Timer software clear instructions and the

third is via a HALT instruction.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle

²CLR WDT² instruction while the second is to use

the two commands

²CLR WDT1² and ²CLR WDT2². For

the first option, a simple execution of

²CLR WDT² will

clear the WDT while for the second option, both

²CLR

WDT1

² and ²CLR WDT2² must both be executed alter-

nately to successfully clear the Watchdog Timer. Note

that for this second option, if

²CLR WDT1² is used to

clear the Watchdog Timer, successive executions of this

instruction will have no effect, only the execution of a

²CLR WDT2² instruction will clear the Watchdog Timer.

Similarly after the

²CLR WDT2² instruction has been ex-

ecuted, only a successive

²CLR WDT1² instruction can

clear the Watchdog Timer.

The maximum time out period is when the 2

15 division ra-

tio is selected. As an example, with a 32.768kHz LXT

oscillator as its source clock, this will give a maximum

watchdog period of around 1 second for the 2

15 division

ratio, and a minimum timeout of 7.8ms for the 2

8 division

ration. If the fSYS/4 clock is used as the Watchdog Timer

clock source, it should be noted that when the system

enters the SLEEP or IDLE0 Mode, then the instruction

clock is stopped and the Watchdog Timer may lose its

protecting purposes. For systems that operate in noisy

environments, using the fSUB clock source is strongly

recommended.

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