HT66F40 datasheet(94/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

October 24, 2011

This is the output control bit for the TM output pin. Its operation depends upon whether TM is

being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is

in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of

the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM

signal is active high or active low.

Bit 2

TnPOL: TPn_0, TPn_1 Output polarity Control

0: Non-invert

1: Invert

This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM

output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the

Timer/Counter Mode.

Bit 1

TnDPX: TMn PWM period/duty Control

0: CCRP - period; CCRA - duty

1: CCRP - duty; CCRA - period

This bit, determines which of the CCRA and CCRP registers are used for period and duty

control of the PWM waveform.

Bit 0

TnCCLR: Select TMn Counter clear condition

0: TMn Comparatror P match

1: TMn Comparatror A match

This bit is used to select the method which clears the counter. Remember that the Compact TM

contains two comparators, Comparator A and Comparator P, either of which can be selected to

clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a

compare match occurs from the Comparator A. When the bit is low, the counter will be cleared

when a compare match occurs from the Comparator P or with a counter overflow. A counter

overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.

The TnCCLR bit is not used in the PWM Mode.

Compact Type TM Operating Modes

The Compact Type TM can operate in one of three oper-

ating modes, Compare Match Output Mode, PWM

Mode or Timer/Counter Mode. The operating mode is

selected using the TnM1 and TnM0 bits in the TMnC1

Compare Match Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

²00² respectively. In this mode

once the counter is enabled and running it can be

cleared by three methods. These are a counter over-

flow, a compare match from Comparator A and a com-

pare match from Comparator P. When the TnCCLR bit is

low, there are two ways in which the counter can be

cleared. One is when a compare match occurs from

Comparator P, the other is when the CCRP bits are all

zero which allows the counter to overflow. Here both

TnAF and TnPF interrupt request flags for the Compara-

tor A and Comparator P respectively, will both be gener-

ated.

If the TnCCLR bit in the TMnC1 register is high then the

counter will be cleared when a compare match occurs

from Comparator A. However, here only the TnAF inter-

rupt request flag will be generated even if the value of

the CCRP bits is less than that of the CCRA registers.

Therefore when TnCCLR is high no TnPF interrupt re-

quest flag will be generated. If the CCRA bits are all

zero, the counter will overflow when its reaches its maxi-

mum 10-bit, 3FF Hex, value, however here the TnAF in-

terrupt request flag will not be generated.

As the name of the mode suggests, after a comparison

is made, the TM output pin will change state. The TM

output pin condition however only changes state when

an TnAF interrupt request flag is generated after a com-

pare match occurs from Comparator A. The TnPF inter-

rupt request flag, generated from a compare match

occurs from Comparator P, will have no effect on the TM

output pin. The way in which the TM output pin changes

state are determined by the condition of the TnIO1 and

TnIO0 bits in the TMnC1 register. The TM output pin can

be selected using the TnIO1 and TnIO0 bits to go high,

to go low or to toggle from its present condition when a

compare match occurs from Comparator A. The initial

condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the

TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero

then no pin change will take place.

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

Timer/Counter Mode operates in an identical way to the

Compare Match Output Mode generating the same in-

terrupt flags. The exception is that in the Timer/Counter

Mode the TM output pin is not used. Therefore the

above description and Timing Diagrams for the Com-

pare Match Output Mode can be used to understand its

function. As the TM output pin is not used in this mode,

the pin can be used as a normal I/O pin or other

pin-shared function.

HT66F40 数据表(PDF) 94 Page - Holtek Semiconductor Inc

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