STTS2002B2DN3F datasheet(31/52 Pages) STMICROELECTRONICS

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STTS2002

SPD EEPROM operation

Doc ID 15389 Rev 5

31/52

Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must

be applied. This voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (tW).

At power-down (phase during which VDD decreases continuously), as soon as VDD drops

from the normal operating voltage below the Power On Reset threshold voltage, the device

stops responding to any instruction sent to it.

5.3

Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 23: Device select code (on serial data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit chip enable

“Address” (A2, A1, A0). To address the memory array, the 4-bit device type identifier is

1010b; to access the write-protection settings, it is 0110b.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a

unique 3-bit code on the chip enable (A0, A1, A2) inputs. When the device select code is

received, the device only responds if the chip enable address is the same as the value on

the chip enable (A0, A1, A2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on serial data (SDA) during the 9th bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into standby mode. The

operating modes are detailed in Table 24.

Table 23.

Device select code

Chip enable

signals

Device type identifier

Chip enable bits

b7(1)

The most significant bit, b7, is sent first.

Memory area select code

(two arrays)(2)

A0, A1 and A2 are compared against the respective external pins on the memory device.

1010

Set write protection

(SWP)

VSS

VHV

0110

0010

Clear write protection

(CWP)

VSS

VDD

VHV

0110

Permanently set write

protection (PSWP)(2)

Read SWP

VSS

VHV

0011

Read CWP

VSS

VDD

VHV

0111

Read PSWP(2)

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