CC2420-RTR1 datasheet(82/92 Pages) TI

82 / 92 page

CC2420

SWRS041B

Page 82 of 89

SFDMUX

Signal output on SFD pin

Description

SFD

Normal operation

ADC_I[0]

ADC, I-branch, LSB used for random number generation

DEMOD_RESYNCH_EARLY

High one 16 MHz clock cycle each time the demodulator

resynchronises early

LOCK_STATUS

Lock status, same as FSCTRL.LOCK_STATUS

MOD_CHIP

Chip rate data signal during transmission

MOD_SERIAL_DATA_OUT

Bit rate data signal during transmission

FFCTRL_FS_PD

Frequency synthesizer power down, active high

FFCTRL_ADC_PD

ADC power down, active high

FFCTRL_VGA_PD

VGA power down, active high

FFCTRL_RXBPF_PD

Receiver bandpass filter power down, active high

FFCTRL_LNAMIX_PD

Receiver LNA / Mixer power down, active high

FFCTRL_PA_P_PD

Power amplifier power down, active high

VGA_PEAK_DET[0]

VGA Peak detector, gain stage 0

VGA_PEAK_DET[2]

VGA Peak detector, gain stage 2

VGA_PEAK_DET[4]

VGA Peak detector, gain stage 4

AGC_LNAMIX_GAINMODE[0]

RF receiver front-end gain mode, bit 0

AGC_VGA_GAIN[0]

VGA gain setting, bit 0

RXBPF_CAL_CLK

Receiver bandpass filter calibration clock

Reserved

PD_F_COMP

Frequency synthesizer frequency comparator value

FSDIG_FREF

Frequency synthesizer, 4 MHz reference signal

FSDIG_FPLL

Frequency synthesizer, 4 MHz divided signal

FSDIG_LOCK_WINDOW

Frequency synthesizer, lock window

WINDOW_SYNC

Frequency synthesizer, synchronized lock window

CLK_ADC_DIG

ADC clock signal 2

ZERO

Low

ONE

High

Table 13. SFD test signal select table

CC2420-RTR1 数据表(PDF) 82 Page - Texas Instruments

CC2420-RTR1 数据表(HTML) 82 Page - Texas Instruments

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