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CC2420-RTR1 数据表(PDF) 28 Page - Texas Instruments |
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CC2420-RTR1 数据表(HTML) 28 Page - Texas Instruments |
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28 / 92 page  CC2420 SWRS041B Page 28 of 89 0 0 A5 A4 A3 A2 A0 A1 D W15 DW14 DW13 D W12 D W11 DW10 D W9 D W8 D W7 D W6 D W5 D W4 D W3 D W2 D W1 D W0 S7 S6 S5 S4 S3 S2 S0 S1 0 1 A5 A4 A3 A2 A0 A1 D R15 D R14 D R13 D R12 D R11 D R10 D R9 D R8 D R7 D R6 D R5 D R4 D R3 D R2 D R1 D R0 S7 S6 S5 S4 S3 S2 S0 S1 Read from register / RXFIFO: Write to register / RXFIFO: X X X X X D R15 SCLK CSn SI SO SI SO t sp t ch t sd t hd t ns t cl 1 A6 A5 A4 A3 A2 A0 A1 B1 B0 0 X X X X X D W7 D W6 D W5 D W4 D W3 D W2 D W1 D W0 S7 S6 S5 S4 S3 S2 S0 S1 1 A6 A5 A4 A3 A2 A0 A1 D R7 D R6 D R5 D R4 D R3 D R2 D R1 D R0 S7 S6 S5 S4 S3 S2 S0 S1 Read one byte from RAM: (multiple reads also possible) Read and write one byte to RAM: (multiple read / writes also possible) X X X X X D R7 B1 B0 1 X X X X X X X SI SO SI SO D R7 D R6 D R5 D R4 D R3 D R2 D R1 D R0 D R7 0 0 A5 A4 A3 A2 A0 A1 D W7 D W6 D W5 D W4 D W3 D W2 D W1 D W0 D W7 D W6 D W5 D W4 D W3 D W2 D W1 D W0 S7 S6 S5 S4 S3 S2 S0 S1 Write to TXFIFO: X X X SI SO S7 S6 S5 S4 S3 S2 S0 S1 S7 S6 S5 S4 S3 S2 S0 S1 S7 Figure 9. SPI timing diagram Parameter Symbol Min Max Units Conditions SCLK , clock frequency FSCLK 10 MHz SCLK low pulse duration tcl 25 ns The minimum time SCLK must be low. SCLK high pulse duration tch 25 ns The minimum time SCLK must be high. CSn setup time tsp 25 ns The minimum time CSn must be low before the first positive edge of SCLK. CSn hold time tns 25 ns The minimum time CSn must be held low after the last negative edge of SCLK. SI setup time tsd 25 ns The minimum time data on SI must be ready before the positive edge of SCLK. SI hold time thd 25 ns The minimum time data must be held at SI, after the positive edge of SCLK. Rise time trise 100 ns The maximum rise time for SCLK and CSn Fall time tfall 100 ns The maximum fall time for SCLK and CSn Note: The set-up- and hold-times refer to 50% of VDD. Table 4. SPI timing specification 13.3 Status byte During transfer of the register access byte, command strobes, the first RAM address byte and data transfer to the TXFIFO, the CC2420 status byte is returned on the SO pin. The status byte contains 6 status bits which are described in Table 5. Issuing a SNOP (no operation) command strobe may be used to read the status byte. It may also be read during access to chip functions such as register or FIFO access. |
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