ADIS16136

Data Sheet

Rev. A | Page 4 of 20

TIMING SPECIFICATIONS

Table 2.

Normal Mode

Parameter

Description

Min1

Typ

Max

Unit

Serial clock

0.01

2.5

MHz

Stall period between data, see Figure 3

15

µs

Read rate

25

µs

Chip select to clock edge

48.8

ns

DOUT valid after SCLK edge

25

ns

DIN setup time before SCLK rising edge

24.4

ns

DIN hold time after SCLK rising edge

48.8

ns

SCLK rise and fall times

5

12.5

ns

DOUT rise and fall times

5

12.5

ns

CS high after SCLK edge

0

ns

Input sync positive pulse width

5

µs

Input sync to data ready output

300

µs

Input sync period

488

µs

Input sync low time

100

µs

1

Guaranteed by design and characterization but not tested in production.

Timing Diagrams

Figure 2. SPI Timing and Sequence

Figure 3. Stall Time and Data Rate

Figure 4. Input Clock Timing Diagram

CS

SCLK

DOUT

DIN

1

2

3

4

5

6

15

16

R/W

A5

A6

A4

A3

A2

D2

MSB

DB14

D1

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

CS

SCLK

SYNC

CLOCK (CLKIN)

DATA

READY