Data Sheet

ADIS16136

Rev. A | Page 11 of 20

DIGITAL PROCESSING CONFIGURATION

Figure 18 provides a block diagram for the sampling and digital

filter stages inside the ADIS16136. Table 15 provides a summary

of registers for sample rate and filter control.

Table 15. Digital Processing Registers

Register Name

Address

Description

SMPL_PRD

0x1E

Sample rate control

AVG_CNT

0x20

Digital filtering and range control

DEC_RATE

0x22

Decimation rate setting

INTERNAL SAMPLE RATE

The SMPL_PRD register in Table 16 provides a programmable

control for the internal sample rate. Use the following formula

to calculate the decimal number for the code to write into this

register:

( )

;1

768

,

32

_

−

=

S

f

PRD

SMPL

The factory default setting for SMPL_PRD sets the internal

sample rate to a rate of 1024 SPS; the minimum setting for the

SMPL_PRD register is 0x000F, which results in an internal

sample rate of 2048 SPS.

Table 16. SMPL_PRD Bit Descriptions

Bits

Description (Default = 0x001F)

[15:0]

INPUT CLOCK CONFIGURATION

Set SMPL_PRD = 0x0000 (DIN = 0x9F00, then DIN = 0x9E00)

to disable the internal clock and enable DIO4/CLKIN as a clock

input pin.

DIGITAL FILTERING

The AVG_CNT register (see Table 17) provides user controls

for the low-pass filter. This filter contains two cascaded averaging

filters that provide a Bartlett window FIR filter response (see

Figure 18). For example, set AVG_CNT[7:0] = 0x04 (DIN =

0xA004) to set each stage to 16 taps. When used with the default

sample rate of 1024 SPS, this establishes a −3 dB bandwidth of

approximately 24 Hz for this filter.

Figure 17. Bartlett Window FIR Filter Frequency Response

Table 17. AVG_CNT Bit Descriptions

Bits

Description (Default = 0x0000)

[15:3]

Don’t care

[2:0]

Binary; B variable in Figure 18; maximum = 110 (6)

0

–20

–40

–60

–80

–100

–120

–140

0.001

0.01

0.1

1

FREQUENCY (

N = 2

N = 4

N = 16

N = 64