ADIS16136

Data Sheet

Rev. A | Page 8 of 20

THEORY OF OPERATION

The ADIS16136 is an autonomous system that requires no user

initialization. As soon as it has a valid power supply, it initializes

and starts sampling, processing, and loading sensor data into

the output registers. After each sample cycle concludes, DIO1

pulses high. The SPI interface enables simple integration with

many embedded processor platforms, as shown in Figure 10

(electrical connection) and Table 6 (processor pin names and

functions).

Figure 10. Electrical Connection Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

IRQ

Interrupt request

MOSI

Master output, slave input

MISO

Master input, slave output

SCLK

Serial clock

The ADIS16136 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 13. Table 7 provides a list of

the most common settings that require attention to initialize a

processor serial port for the ADIS16136 SPI interface.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16136 operates as a slave

SCLK Rate ≤ 2 MHz

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence

16-Bit Mode

Shift register/data length

READING SENSOR DATA

A single register read requires two 16-bit SPI cycles. The first

cycle requests the contents of a register using the bit assignments

in Figure 13. Then, the register contents follow on DOUT during

the second sequence. Figure 11 includes three single register reads

in succession. In this example, the process starts with Pin 5,

DIN = 0x0600, to request the contents of the GYRO_OUT

register and follows with 0x0400 to request the contents of the

GYRO_OUT2 register and with 0x0200 to request the contents

of the TEMP_OUT register. Full duplex operation enables pro-

cessors to use the same 16-bit SPI cycle to read data from DOUT

while requesting the next set of data on the DIN pin. Figure 12

provides an example of the four SPI signals when reading

GYRO_OUT in a repeating pattern.

Figure 11. SPI Read Example

Figure 12. SPI Read Example, Second 16-Bit Sequence

Figure 13. SPI Communication Bit Sequence

SYSTEM

PROCESSOR

SPI MASTER

ADIS16136

SCLK

CS

DIN

DOUT

SCLK

SS

MOSI

MISO

5V

IRQ

DIO1

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V OR 5V LOGIC LEVELS

10

6

3

5

4

7

11

12

13

14

15

DIN

DOUT

0x0600

0x0400

0x0200

GYRO_OUT

GYRO_OUT2

TEMP_OUT

DOUT = 1111 1001 1101 1010 = 0xF9DA = –1574 LSBs = –29.765°/sec

DIN = 0000 0110 0000 0000 = 0x0600

CS

SCLK

DIN

DOUT

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH-IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.