ADIS16136

Data Sheet

Rev. A | Page 16 of 20

Table 31. MSC_CTRL Bit Descriptions

Bits

Description (Default = 0x0006)

[15:12]

Not used

11

Memory test (cleared upon completion)

(1 = enabled, 0 = disabled)

10

Automatic self test (cleared upon completion)

(1 = enabled, 0 = disabled)

9

Manual self test

(1 = enabled, 0 = disabled)

8

Not used

7

Disable sensor compensation

(1 = disable compensation, 0 = enable compensation)

[6:3]

Not used

2

Data ready enable

(1 = enabled, 0 = disabled)

1

Data ready polarity

(1 = active high, 0 = active low)

0

Data ready line select

(1 = DIO2, 0 = DIO1)

Table 32. GPIO_CTRL Bit Descriptions

Bits

Description (Default = 0x0000)

[15:12]

Don’t care

11

General-Purpose I/O Line 4 (DIO4) data level

10

General-Purpose I/O Line 3 (DIO3) data level

9

General-Purpose I/O Line 2 (DIO2) data level

8

General-Purpose I/O Line 1 (DIO1) data level

[7:4]

Don’t care

3

General-Purpose I/O Line 2 (DIO2) direction control

(1 = output, 0 = input)

2

General-Purpose I/O Line 1 (DIO1) direction control

(1 = output, 0 = input)

1

General-Purpose I/O Line 2 (DIO2) direction control

(1 = output, 0 = input)

0

General-Purpose I/O Line 1 (DIO1) direction control

(1 = output, 0 = input)

SELF TEST

The MSC_CTRL bits (see Table 31) provide a self test function

that helps verify the mechanical integrity of the MEMS and

signal processing circuit. When enabled, the self test applies an

electrostatic force to the internal sensor element, which causes it

to move in a manner that simulates its response to actual rotation.

There are two self test options in the MSC_CTRL register: auto-

matic and manual. Set MSC_CTRL[10] = 1 (DIN = 0x9D04) to

run the automatic self test routine, which reports a pass/fail result

in DIAG_STAT[5]. MSC_CTRL[10] resets itself to 0 after com-

pleting this routine. This process takes approximately 45 ms. Set

MSC_CTRL[9] = 1 (DIN = 9D02) to manually activate the self test

function, and set MSC_CTRL[9] = 0 (DIN = 9D00) to manually

deactivate the self test function. Measure the output bias for each

condition, calculate the difference between them, and compare

it to the expected self test response shown in Table 1.

POWER MANAGEMENT

The SLP_CTRL register (see Table 33) provides two different

sleep modes for system level management: normal and timed.

Set SLP_CTRL[7:0] = 0xFF (DIN = 0xA4FF) to start normal

sleep mode. To awaken the device from sleep mode, use one of

the following options to restore normal operation: assert CS from

high to low, pulse RST low, then high again, or cycle the power. Use

SLP_CTRL[7:0] to put the device into sleep mode for a specified

period. For example, SLP_CTRL[7:0] = 0x64 (DIN = 0xA464)

puts the ADIS16136 to sleep for 50 sec.

Table 33. SLP_CTRL Bit Descriptions

Bits

Description

[15:8]

Not used

[7:0]

0xFF: normal sleep mode

0x00 to 0xFE: programmable sleep time bits; 0.5 sec/LSB

STATUS

The DIAG_STAT register (see Table 34) provides error flags for

a number of functions. Each flag uses a 1 to indicate an error

condition and a 0 to indicate a normal condition. Reading this

register provides access to the status of each flag and resets all of

the bits to 0 for monitoring future operation. If the error

condition remains, the error flag returns to 1 at the conclusion

of the next sample cycle. The SPI communication error flag in

DIAG_STAT[3] indicates that the number of SCLKs in a SPI

sequence did not equal a multiple of 16 SCLKs.

Table 34. DIAG_STAT Bit Descriptions

Bits

Description (Default = 0x0000)

[15:10]

Not used

9

Alarm 2 status (1 = active, 0 = inactive)

8

Alarm 1 status (1 = active, 0 = inactive)

7

Not used

6

Flash test, checksum flag (1 = fail, 0 = pass)

5

Self test diagnostic error flag (1 = fail, 0 = pass)

4

Sensor over range (1 = over range, 0 = normal)

3

SPI communication failure (1 = fail, 0 = pass)

2

Flash update failure (1 = fail, 0 = pass)

[1:0]

Not used